Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Patent metadata

Field	Value
Publication number	US-10719237-B2
Application number	US-201614992979-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Jan 11, 2016
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

First claim

What is claimed is:

1. An apparatus, comprising:
a non-volatile memory array comprising a plurality of partitions, wherein each of the plurality of partitions comprises a respective plurality of memory cells;
a plurality of local controllers, wherein each of the plurality of local controllers is configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command; and
a controller configured to provide the plurality of memory access commands according to separation timing rules for the memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands, the controller further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition;
wherein the controller is further configured to send a first memory access command of a first type to a first target partition via a respective local controller associated with the first target partition when:
a memory access command preceding the first memory access command is a second type different from the first type and is sent by the controller to the first target partition via the respective local controller associated with the first target partition, and
at least a first minimum timing between the first memory access command and the memory access command preceding the first memory access command is met;

wherein the controller is further configured to send a second memory access command of the second type to the first target partition via the respective local controller associated with the first target partition when:
a memory access command preceding the second memory access command is the first type and is sent by the controller to the first target partition via the respective local controller associated with the first target partition, and
at least a second minimum timing between the second memory access command and the memory access command preceding the second memory access command is met, wherein the second minimum timing is different from the first minimum timing;

wherein the controller is further configured to send a third write memory access command to a third target partition via a respective local controller associated with the third target partition when:
a write memory access command preceding the third write memory access command is sent by the controller to the third target partition via the respective local controller associated with the third target partition, and
at least a third minimum timing between the third write memory access command and the write memory access command preceding the third write memory access command is met; and

wherein the controller is further configured to send a fourth write memory access command to the third target partition via the respective local controller associated with the third target partition when:
a write memory access command preceding the fourth write memory access command is sent by the controller to a fourth target partition via a respective local controller associated with the fourth target partition, and
at least a fourth minimum timing between the fourth write memory access command and the write memory access command preceding the fourth write memory access command is met, wherein the fourth minimum timing is different from the third minimum timing such that the write memory access command preceding the fourth write memory access command is concurrently being processed at the fourth target partition while the fourth write memory access command is sent to the third target partition.

2. The apparatus of claim 1 , wherein a local controller of the plurality of local controller comprises:
respective sense amplifiers configured to sense data during execution of the memory access command;
respective drivers configured to drive voltages along access lines; and
respective sequencers configured to execute an algorithm associated with the memory access command.

3. The apparatus of claim 1 , wherein the controller comprises a command and address user interface circuit configured to determine a memory access command type and the respective target partition of the plurality of target partitions for each of the plurality of memory access commands.

4. The apparatus of claim 3 , wherein the controller further comprises a command and address interface circuit configured to receive each of the plurality of memory access commands from a memory controller and to provide each of the plurality of memory access commands to the command and address user interface circuit.

5. The apparatus of claim 1 , further comprising a plurality of data buffers, wherein each of the plurality of data buffers is configured to independently and concurrently receive data from or provide data to a respective one of the plurality of partitions.

6. The apparatus of claim 1 , wherein the controller further comprises a data input/output interface circuit configured to receive write data from a memory controller and to provide the write data to the data block or to receive read data from the data block and to provide the read data to the memory controller.

7. An apparatus, comprising:
a non-volatile memory comprising a plurality of partitions and a plurality of local controllers, wherein each of the plurality of local controllers is configured to independently access a respective one of the plurality of partitions, wherein each of the plurality of partitions comprises a respective plurality of memory cells;
a memory controller configured to provide memory access commands to the non-volatile memory according to separation timing rules for the memory access commands, wherein the memory controller is configured to provide a first memory access command of a first type to a first partition of the plurality of partitions, and provide a second memory access command of second type different from the first type to the first partition of the plurality of partitions immediately after the first memory access command at a minimum of a first time after the first memory access command, and the memory controller is further configured to provide a third memory access command of the second type to a second partition of the plurality of partitions, and provide a fourth memory access command of the first type to the second partition immediately after the third memory access command at a minimum of a second time after the third memory access command is sent, wherein the first time is different from the second time;
wherein the memory controller is further configured to provide a fifth write memory access command to a fifth target partition via a respective local controller associated with the fifth target partition when:
a write memory access command preceding the fifth write memory access command is provided by the memory controller to the fifth target partition via the respective local controller associated with the fifth target partition, and
at least a third time after the write memory access command preceding the fifth write memory access command is passed; and

wherein the controller is further configured to send a sixth write memory access command to the fifth target partition via the respective local controller associated with the fifth target partition when:
a write memory access command preceding the sixth write memory access command is provided by the controller to a sixth target partition via a respective local controller associated with the sixth target partition, and
at least a fourth time after the write memory access command preceding

Assignees

• Micron Technology Inc

Inventors

• Sundaram Rajesh
• Kau Derchang
• Jungroth Owen W
• Chu Daniel
• Zeng Raymond W
• Qawami Shekoufeh

Classifications

• G11C7/1042

  using interleaving techniques, i.e. read-write of one part of the memory while preparing another part · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title