Efficient transport flow processing on an accelerator

Patent metadata

Field	Value
Publication number	US-10715451-B2
Application number	US-201615146013-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	May 7, 2015
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

First claim

The invention claimed is:

1. Data processing apparatus, comprising:
a host processor, configured with a transport layer stack which processes received packets;
a network interface controller (NIC), which is configured to couple the host processor to a packet data network;
a memory, configured to hold a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network; and
acceleration logic, which is coupled to the host processor through a host bus, a network switch or a network link, and is configured to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table,
wherein the NIC is configured to steer incoming packets from the packet data network to the acceleration logic,
wherein the acceleration logic is configured to store payloads of the incoming packets in a temporary buffer, to forward headers of the incoming packets to the host, through the host bus, the network switch or the network link, for processing by the transport layer stack in the host processor and to perform the computational operations on the stored payloads of packets, responsively to results of the processing by the transport layer stack provided to the acceleration logic,
wherein the host processor is configured to feed the transport layer stack with packets formed of the forwarded headers and padding to the original sizes of the packets.

2. The apparatus according to claim 1 , wherein the acceleration logic and the memory are comprised in an acceleration device, which is coupled between the NIC and the packet data network.

3. The apparatus according to claim 2 , and comprising a switch, which is coupled between the NIC and the acceleration device and is configured to be coupled to communicate with multiple host processors, wherein the flow state table contains context information with respect to the packet flows conveyed via the acceleration device to and from the multiple host processors.

4. The apparatus according to claim 1 , wherein the acceleration logic is coupled to the host processor and the NIC via a host bus, and wherein the NIC is configured to steer the packets received from the packet data network in the multiple packet flows via the host bus to the acceleration logic for performance of the computation operations thereon.

5. The apparatus according to claim 1 , wherein at least one of the host processor and the NIC is configured to apply tags to the packets for transmission to the packet data network, wherein the tags are indicative of the computational operations to be performed by the acceleration logic, and wherein the acceleration logic is configured to decide on the computational operations to be applied to each of the packets that it receives from the NIC responsively to the tags.

6. The apparatus according to claim 1 , wherein the computational operations performed by the acceleration logic comprise cryptographic computations, and wherein the context information comprises cryptographic parameters.

7. The apparatus according to claim 1 , wherein the flow state table indicates for the flows a current sequence number and wherein the acceleration logic is configured to determine whether packets received from the network have a sequence number matching the current sequence number of the flow of the packet in the flow state table, and to perform the computational operations only on packets for which the packet sequence number matches the current sequence number in the flow state table.

8. The apparatus according to claim 7 , wherein the acceleration logic is configured to pass to the host processor packets for which the packet sequence number does not match the current sequence number in the corresponding flow state table, without performing the computational operations.

9. The apparatus according to claim 8 , wherein the acceleration logic is configured, in response to detecting a packet received from the network for which the packet sequence number does not match the corresponding current sequence number of the flow of the packet in the flow state table, to pass to the host processor the corresponding context information for the packet from the flow state table.

10. The apparatus according to claim 8 , wherein the host processor is configured to reorder packets passed from the acceleration logic without performing the computational operations, and to return the reordered packets to the acceleration logic for performing the computational operations.

11. The apparatus according to claim 1 , wherein the host processor is configured to pass to the acceleration logic, for packets processed by the transport layer stack, a descriptor identifying the packet, and wherein the acceleration logic is configured perform the computational operations responsively to the passed descriptor.

12. The apparatus according to claim 1 , wherein the acceleration logic is configured to forward the headers of the incoming packets with descriptors pointing to the stored payload.

13. The apparatus according to claim 1 , wherein the acceleration logic is configured to forward headers of the incoming packets to the host through a network switch.

14. The apparatus according to claim 1 , wherein the acceleration logic is configured to forward headers of the incoming packets to the host through a host bus.

15. The apparatus according to claim 1 , wherein the acceleration logic is configured to forward headers of the incoming packets to the host through a network link.

16. A method for data processing, comprising:
coupling a computational accelerator to communicate with a host processor through a host bus, a network switch or a network link, wherein the host processor is coupled to transmit and receive data packets to and from a packet data network, wherein the host processor is configured with a transport layer stack which processes received packets;
storing in a memory a flow state table containing context information with respect to computational operations to be performed by the computational accelerator on multiple packet flows conveyed between the host processor and the packet data network;
steering incoming packets from the packet data network to the computational accelerator;
storing payloads of the incoming packets in a temporary buffer, by the computational accelerator;
forwarding headers of the incoming packets from the computational accelerator to the host through the host bus, the network switch or the network link, for processing by the transport layer stack in the host processor;
feeding the transport layer stack with packets formed of the forwarded headers and padding to the original sizes of the packets; and
performing, by the computational accelerator, the computational operations on the stored payloads of packets, responsively to results of the processing by the transport layer stack in the host processor, provided to the computational accelerator.

17. The method according to claim 16 , wherein the host processor is coupled to transmit and receive the data packets via a network interface controller (NIC), and wherein the computational accelerator is coupled between the NIC and the packet data network.

18. The method according to claim 17 , wherein coupling the computational accelerator comprises configuring the computational accelerator to communicate via a switch with multiple host processors, wherein the flow state table contains context information with respect to the packet flows co

Assignees

• Mellanox Technologies Ltd

Inventors

• Raindel Shachar
• Raikin Shlomo
• Liss Liran

Classifications

• H04L67/63

  Routing a service request depending on the request content or context · CPC title

• H04L63/0485

  Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up · CPC title

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04L63/0428 Primary

  wherein the data content is protected, e.g. by encrypting or encapsulating the payload · CPC title

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title