Gate driving circuit and power supply circuit

Patent metadata

Field	Value
Publication number	US-10715026-B2
Application number	US-201916372624-A
Country	US
Kind code	B2
Filing date	Apr 2, 2019
Priority date	Apr 7, 2017
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

A gate driving circuit includes a first transistor, a first control circuit that changes a gate voltage of the first transistor from a low level to a high level, and a second control circuit that changes the gate voltage of the first transistor from the high level to the low level, wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.

First claim

What is claimed is:

1. A gate driving circuit comprising:
a first transistor;
a first control circuit that changes a gate voltage of the first transistor from a low level to a high level;
a second control circuit that changes the gate voltage of the first transistor from the high level to the low level; and
a protecting circuit that suppresses overshoot of the gate voltage output by the first control circuit and does not suppress undershoot of the gate voltage output by the second control circuit,
wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.

2. The gate driving circuit according to claim 1 , further comprising:
a first diode that includes an anode coupled to an output terminal of the first control circuit and a cathode coupled to the gate of the first transistor; and
a second diode that includes an anode coupled to the gate of the first transistor and a cathode coupled to an output terminal of the second control circuit.

3. The gate driving circuit according to claim 1 , further comprising:
a first shaping circuit that shapes a rising edge of the gate voltage output by the first control circuit; and
a second shaping circuit that shapes a falling edge of the gate voltage output by the second control circuit.

4. The gate driving circuit according to claim 1 , wherein the first control circuit and the second control circuit are synchronized with a drain voltage of the first transistor to generate the gate voltage.

5. The gate driving circuit according to claim 1 , further comprising:
a clock generating circuit coupled to the first control circuit and the second control circuit.

6. A power supply circuit comprising:
a transformer including a primary winding and a secondary winding;
a first diode coupled to the secondary winding;
a first transistor coupled to the first diode in parallel;
a first control circuit that changes a gate voltage of the first transistor from a low level to a high level;
a second control circuit that changes the gate voltage of the first transistor from the high level to the low level; and
a protecting circuit that suppresses overshoot of the gate voltage output by the first control circuit and does not suppress undershoot of the gate voltage output by the second control circuit,
wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.

7. The power supply circuit according to claim 6 , wherein the first control circuit and the second control circuit are synchronized with a drain voltage of the first transistor to generate the gate voltage.

8. A power supply circuit comprising:
a transformer including a primary winding and a secondary winding;
a first transistor coupled to the primary winding;
a first control circuit that changes a gate voltage of the first transistor from a low level to a high level;
a second control circuit that changes the gate voltage of the first transistor from the high level to the low level; and
a protecting circuit that suppresses overshoot of the gate voltage output by the first control circuit and does not suppress undershoot of the gate voltage output by the second control circuit,
wherein the first control circuit and the second control circuit are coupled to each other in parallel with respect to a gate of the first transistor.

9. The power supply circuit according to claim 8 , further comprising:
a clock generating circuit coupled to the first control circuit and the second control circuit.

Assignees

• Fujitsu Ltd

Inventors

• Hirose Tatsuya

Classifications

• H02M1/348

  Passive dissipative snubbers · CPC title

• H02M1/344

  Active dissipative snubbers · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M1/34 Primary

  Snubber circuits · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title