Array substrate and display device

Patent metadata

Field	Value
Publication number	US-10714510-B2
Application number	US-201816201771-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	Nov 27, 2017
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

An array substrate includes: a base substrate; at least one first connection terminal, at least one second connection terminal, and at least one connection line, which are disposed on the base substrate and located in a non-display area of the array substrate, the at least one connection line being connected with the at least one first connection terminal and the at least one second connection terminal; at least one gate line disposed on the base substrate and located in a display area of the array substrate. The first connection terminal is for connecting with an IC, and the second connection terminal is for connecting with a flexible circuit board. A resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
at least one first connection terminal, at least one second connection terminal, and at least one connection line, which are disposed on the base substrate and located in a non-display area of the array substrate, the at least one connection line being connected with the at least one first connection terminal and the at least one second connection terminal;
at least one gate line disposed on the base substrate and located in a display area of the array substrate, and
at least one first metal line disposed on the base substrate and located in the display area of the array substrate, wherein
the at least one first connection terminal is configured to connect with an integrated circuit (IC);
the at least one second connection terminal is configured to connect with a flexible circuit board;
a resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line, and a resistivity of the at least one first metal line is less than a resistivity of the at least one gate line;
each of the at least one connection line comprises a first connection sub-line, a third connection sub-line and a second connection sub-line electrically connected in sequence, the first connection sub-line is electrically connected with corresponding one or more first connection terminals of the at least one first connection terminal, and the second connection sub-line is electrically connected with corresponding one or more second connection terminals of the at least one second connection terminal; and
the first connection sub-line, the second connection sub-line and the at least one gate line are disposed in a same layer, and are made of a same material; the third connection sub-line and the at least one first metal line are disposed in a same layer, and are made of a same material.

2. The array substrate according to claim 1 , wherein
the array substrate further comprises an insulating layer disposed between the first and second connection sub-lines and the third connection sub-line;
the at least one first connection terminal, the at least one second connection terminal and the third connection sub-line are all located at a side of the insulating layer away from the base substrate; the first connection sub-line and the second connection sub-line are both located at an opposite side of the insulating layer close to the base substrate; wherein,
each of the at least one first connection terminal is connected to a corresponding first connection sub-line by passing through at least one first via hole formed in the insulation layer;
each of the at least one second connection terminal is connected to a corresponding second connection sub-line by passing through at least one second via hole formed in the insulation layer;
the third connection sub-line is connected to a corresponding first connection sub-line by passing through at least one third via hole formed in the insulation layer; and the third connection sub-line is connected to a corresponding second connection sub-line by passing through at least one fourth via hole formed in the insulation layer.

3. The array substrate according to claim 2 , further comprising at least one of:
at least one first thin film transistor disposed at a junction of the second connection sub-line and the third connection sub-line, or, at least one second thin film transistor disposed at a junction of the first connection sub-line and the third connection sub-line,
wherein a gate of each first thin film transistor is connected to a corresponding second connection sub-line, and a first electrode and a second electrode of each first thin film transistor are connected to a corresponding third connection sub-line;
wherein a gate of each second thin film transistor is connected to a corresponding first connection sub-line, and a first electrode and a second electrode of each second thin film transistor are connected to a corresponding third connection sub-line.

4. The array substrate according to claim 3 , wherein
a width to length ratio of each of at least one of the at least one first thin film transistor is 20:7.5.

5. The array substrate according to claim 3 , wherein,
a width to length ratio of each of at least one of the at least one second thin film transistor is 20:7.5.

6. The array substrate according to claim 1 , further comprising at least one of:
at least one first connection strip disposed on the base substrate and located in the non-display area of the array substrate; or, at least one second connection strip disposed on the base substrate and located in the non-display area of the array substrate,
wherein the at least one second connection terminal comprises at least two second connection terminals, each first connection strip is disposed between two adjacent second connection terminals that transmit a same signal among the at least two second connection terminals, and each first connection strip is in contact with both of corresponding two adjacent second connection terminals;
wherein the at least one first connection terminal comprises at least two first connection terminals, each second connection strip is disposed between two adjacent first connection terminals that transmit a same signal among the at least two first connection terminals, and each second connection strip is in contact with both of corresponding two adjacent first connection terminals.

7. The array substrate according to claim 6 , wherein
in a case where the array substrate further comprises the at least one first connection strip, each second connection terminal comprises at least one layer in a thickness direction, and the at least one first connection strip and at least one layer of each second connection terminal are disposed in a same layer, and are made of a same material.

8. The array substrate according to claim 1 , wherein at least one whole connection line of the at least one connection line, and the at least one first metal line are disposed in a same layer and are made of a same material.

9. The array substrate according to claim 8 , further comprising an insulating layer disposed on the base substrate and located in the non-display area, wherein
the at least one first connection terminal and the at least one second connection terminal are both located at a side of the insulating layer, and the at least one connection line is located at an opposite side of the insulating layer;
each of the at least one first connection terminal is connected to a corresponding connection line by passing through at least one fifth via hole formed in the insulation layer, and each of the at least one second connection terminal is connected to a corresponding connection line by passing through at least one sixth via hole formed in the insulation layer.

10. The array substrate according to claim 9 , wherein, the at least one first connection terminal and the at least one second connection terminal are both located at a side of the insulation layer away from the base substrate, and the at least one connection line is located at an opposite side of the insulation layer close to the base substrate.

11. The array substrate according to claim 1 , wherein each first metal line is a data line or a common electrode line.

12. The array substrate according to claim 1 , wherein
each first metal line has a laminated structure and comprises at least two layers along a thickness direction, and the at least two layers comprises a layer of Al, and a layer of Ti;
a material of each gate line is Mo.

13. The array substrate according

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Cong Lele
• Sun Jian
• Wang Zhengkui
• Qin Wenwen
• Zhang Jianjun

Classifications

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/443 Primary

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/1222

  Electricity · mapped topic