Elbow contact for field-effect transistor and manufacture thereof

Patent metadata

Field	Value
Publication number	US-10707148-B2
Application number	US-201916587980-A
Country	US
Kind code	B2
Filing date	Sep 30, 2019
Priority date	Nov 17, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

First claim

What is claimed is:

1. A field-effect transistor (FET) including a planar source region and a planar drain region, the FET comprising:
free-standing epitaxial pillars with a hollow core,
wherein the pillars are cladded and grown from a surface of the planar source region and the planar drain region through an oxide layer.

2. A method of manufacture of a contact for a field-effect transistor (FET) including a planar source region and a planar drain region, and a semiconductor structure formed on a top of the planar source region and the planar drain region, the method comprising:
increasing a contact area using a vertical dimension between gates to form an elbow contact by:
growing free-standing epitaxial pillars with a hollow core, through an oxide layer, by patterning a mask over the planar source region and the planar drain region of the device; and
during the growing, using a growth chamber to grow the pillars perpendicular to the semiconductor structure.

3. The method of claim 2 , wherein the pillars are formed by one of:
epitaxial growth;
etching a highly doped Si region; and
recrystallizing a highly doped amorphous semiconductor region.

4. The method of claim 2 , wherein the hollow core is formed by etching a center core of the free-standing epitaxial pillars.

5. A method of manufacture of a contact for a field-effect transistor (FET), the method comprising:
patterning a mask above a source and drain of a FET to form holes in said mask;
growing epitaxial structures having a hollow core from the holes in said mask; and
growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

Assignees

• IBM

Inventors

• Cohen Guy
• Lavoie Christian
• Ozcan Ahmet Serkan
• Solomon Paul

Classifications

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W20/058

  by depositing on sacrificial masks, e.g. using lift-off · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title