Elbow contact for field-effect transistor and manufacture thereof

Patent metadata

Field	Value
Publication number	US-10541191-B2
Application number	US-201715816913-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	Nov 17, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A field-effect transistor (FET) and method of manufacture thereof include a gate, a doped semiconductor structure formed on top of the planar source and drain regions, and a sheath of conducting materials flanking the formed doped semiconductor structure, where the sheath is perpendicular to a surface of the planar source and drain regions.

First claim

What is claimed is:

1. A field-effect transistor (FET) including planar source and drain regions, the FET comprising:
a gate;
a doped semiconductor structure formed on top of the planar source and drain regions; and
a sheath of conducting materials flanking the doped semiconductor structure,
wherein the sheath is perpendicular to a surface of the planar source and drain regions,
wherein the sheath is bent up, out of plane alongside the gate, to thereby increase a contact area,
wherein more than one sheath are present per contact of the doped semiconductor structure,
wherein the planar source and drain regions include a trench,
wherein the trench includes an elongated pillar extending in a direction of growth through the trench,
wherein a core of the trench is removed and replaced with a metal, and
wherein an outside of the elongated pillar includes a metal coating.

2. The FET of claim 1 , wherein the sheath is alongside the gate, and
wherein the sheath is vertical.

3. The FET of claim 1 , wherein the doped semiconductor structure is formed by one of:
epitaxial growth;
etching a highly doped Si region; and
recrystallizing a highly doped amorphous semiconductor region.

4. The FET of claim 1 , wherein the sheath increases the contact area between the doped semiconductor structure and an upper metallization thereby lowering a contact resistance.

5. The FET of claim 1 , wherein the sheath has a non-uniform thickness.

6. The FET of claim 1 , wherein the sheath flanks both sides of the doped semiconductor structure.

Assignees

• IBM

Inventors

• Cohen Guy
• Lavoie Christian
• Ozcan Ahmet Serkan
• Solomon Paul

Classifications

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W20/058

  by depositing on sacrificial masks, e.g. using lift-off · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title