Dynamic reference scheme for improving read margin of resistive memory array

Patent metadata

Field	Value
Publication number	US-10706904-B2
Application number	US-201816234876-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Jan 3, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.

First claim

The invention claimed is:

1. A method of providing a reference voltage for reading of a resistive memory array, the method comprising the steps of:
generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and
generating a second reference voltage when the bitline is in a second resistance state;
wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state;
wherein generating the first and second reference voltages comprises applying a gain to a voltage of the bitline; and
wherein the gain is chosen such that a bit error rate for reading in the first resistance state of the bitline is substantially the same as a bit error rate for reading in the second resistance state.

2. The method of claim 1 , wherein in the first resistance state the bitline exhibits a lower resistance compared to in the second resistance state, and the first reference voltage is larger than the second reference voltage.

3. The method of claim 1 , wherein the gain is smaller than 1.

4. The method of claim 1 , comprising supply voltage scaling of an amplifier circuit for applying the gain to control read energy.

5. The method of claim 1 , further comprising applying an assist technique for improving read robustness.

6. The method of claim 5 , wherein manipulating the assist technique comprises boosting the bitline voltage.

7. The method of claim 6 , further comprising buffering the first or second reference voltage.

8. The method of claim 7 , further comprising turning off a circuit for generating the first and second references voltages during sampling of the resistive memory array.

9. A read circuit for reading of a resistive memory array, the circuit comprising:
a reference voltage generating circuit for generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and for generating a second reference voltage when the bitline is in a second resistance state, wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state;
wherein the reference voltage generating circuit applies a gain to a voltage of the bitline in generating the first and second reference voltages; and
wherein the gain is chosen such that a bit error rate for reading in the first resistance state of the bitline is substantially the same as a bit error rate for reading in the second resistance state.

10. The read circuit of claim 9 , wherein in the first resistance state the bitline exhibits a lower resistance compared to in the second resistance state, and the first reference voltage is larger than the second reference voltage.

11. The read circuit of claim 9 , wherein the gain is smaller than 1.

12. The read circuit of claim 9 , wherein the reference voltage generating circuit is configured for supply voltage scaling to control read energy.

13. The read circuit of claim 9 , further comprising an assist circuit for applying an assist technique for improving read robustness.

14. The read circuit of claim 13 , wherein the assist circuit boosts the bitline voltage.

15. The read circuit of claim 14 , further comprising a buffer for buffering the first or second reference voltage.

16. The read circuit of claim 15 , wherein the reference voltage generating circuit is configured for turn off during sampling of the resistive memory array.

Assignees

• Nat Univ Singapore
• Agency Science Tech & Res
• Agency Fpr Science Tech And Research

Inventors

• Trinh Quang Kien
• Alioto Massimo
• Ruocco Sergio

Classifications

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title