Semiconductor memory device and operation method thereof

Patent metadata

Field	Value
Publication number	US-2015194210-A1
Application number	US-201514666360-A
Country	US
Kind code	A1
Filing date	Mar 24, 2015
Priority date	Aug 3, 2012
Publication date	Jul 9, 2015
Grant date	—

Abstract

A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a memory cell array including a plurality of first lines disposed on a substrate, a plurality of second lines disposed intersecting the first lines, and memory cells disposed at each of intersections of the first lines and the second lines and each configured having a variable resistance element; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively, such that a first potential difference is applied to a selected memory cell disposed at the intersection of the selected first line and the selected second line, the control circuit including a detection circuit configured to, during the setting operation, detect a transition of a resistance state of the selected memory cell using a reference voltage, and the control circuit being configured to, before the setting operation, execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line.

2 . The semiconductor memory device according to claim 1 , wherein
the control circuit is configured to, when executing the setting operation on a plurality of the selected memory cells, execute the read operation and the setting operation on each single one of the selected memory cells.

3 . The semiconductor memory device according to claim 1 , wherein
the control circuit is configured to, before the setting operation on a plurality of the selected memory cells, detect voltage values of a plurality of the selected second lines by a plurality of times of the read operation.

4 . The semiconductor memory device according to claim 1 , wherein
a plurality of the memory cell arrays are stacked in a direction perpendicular to the substrate.

5 . The semiconductor memory device according to claim 1 , wherein
the variable resistance element changes from a high-resistance state to a low-resistance state by the first potential difference.

6 . The semiconductor memory device according to claim 1 , wherein
the control circuit sets the reference voltage based on a voltage value of the selected second line during the read operation.

7 . The semiconductor memory device according to claim 1 , wherein
the third voltage and the fourth voltage are an identical voltage.

8 . A semiconductor memory device, comprising:
a memory cell array including a plurality of first lines disposed on a substrate, a plurality of second lines disposed intersecting the first lines, and memory cells disposed at each of intersections of the first lines and the second lines and each configured having a variable resistance element; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively, such that a first potential difference is applied to a selected memory cell disposed at the intersection of the selected first line and the selected second line, the control circuit including a detection circuit configured to, during the setting operation, detect a transition of a resistance state of the selected memory cell using a reference voltage, and the control circuit being configured capable of changing the reference voltage.

9 . The semiconductor memory device according to claim 8 , wherein
the control circuit is configured to, when executing the setting operation on a plurality of the selected memory cells, change the reference voltage for each single one of the selected memory cells.

10 . The semiconductor memory device according to claim 8 , wherein
the control circuit is configured to, when executing the setting operation on a plurality of the selected memory cells, set the reference voltage for each of the selected second lines to which the selected memory cells are connected.

11 . The semiconductor memory device according to claim 8 , wherein
a plurality of the memory cell arrays are stacked in a direction perpendicular to the substrate.

12 . The semiconductor memory device according to claim 8 , wherein
the variable resistance element changes from a high-resistance state to a low-resistance state by the first potential difference.

13 . The semiconductor memory device according to claim 8 , wherein
the third voltage and the fourth voltage are an identical voltage.

14 . A method of operating a semiconductor memory device,
the semiconductor memory device comprising a memory cell array including a plurality of first lines disposed on a substrate, a plurality of second lines disposed intersecting the first lines, and memory cells disposed at each of intersections of the first lines and the second lines and each configured having a variable resistance element, and the semiconductor memory device configured to execute a setting operation in which a first voltage is applied to a selected first line, a second voltage having a voltage value which is smaller than that of the first voltage is applied to a selected second line, and a third voltage and a fourth voltage are applied to a non-selected first line and a non-selected second line, respectively, such that a first potential difference is applied to a selected memory cell disposed at the intersection of the selected first line and the selected second line, the method comprising: before the setting operation, executing a read operation in which the third voltage is applied to the selected first line and the non-selected first line, the second voltage is applied to the selected second line, and the fourth voltage is applied to the non-selected second line; and during the setting operation, detecting a transition of a resistance state of the selected memory cell using a reference voltage.

15 . The method of operating a semiconductor memory device according to claim 14 , wherein
when the setting operation is executed on a plurality of the selected memory cells, the read operation and the setting operation are executed on each single one of the selected memory cells.

16 . The method of operating a semiconductor memory device according to claim 14 , wherein
before the setting operation on a plurality of the selected memory cells, voltage values of a plurality of the selected second lines are detected by a plurality of times of the read operation.

17 . The method of operating a semiconductor memory device according to claim 14 , wherein
the variable resistance element changes from a high-resistance state to a low-resistance state by the first potential difference.

18 . The method of operating a semiconductor memory device according to claim 14 , wherein
before the setting operation, the reference voltage is set based on a voltage value of the selected second line during the read operation.

19 . The method of operating a semiconductor memory device according to claim 14 , wherein
the third voltage and the fourth voltage are an identical voltage.

Assignees

• Toshiba Kk

Inventors

• Kobayashi Shigeki
• Yamaguchi Takeshi

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title