Fragment compression for coarse pixel shading

Patent metadata

Field	Value
Publication number	US-10706616-B2
Application number	US-201715493214-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.

First claim

What is claimed is:

1. A graphics processing unit comprising:
a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel pipeline; and
a render cache to store coarse pixel data for input to and output from a post-shader pixel processing unit of the pixel pipeline, the render cache including a merge unit to merge a pixel quad read from memory into a coarse pixel, the coarse pixel to be processed by the post-shader pixel processing unit.

2. The graphics processing unit as in claim 1 , wherein the processing cluster is configurable to adjust a scale factor of a coarse pixel during the coarse pixel shading.

3. The graphics processing unit as in claim 1 , wherein the pixel pipeline includes a fragment compression unit to implement cacheline aware fragment compression.

4. The graphics processing unit as in claim 3 , wherein the fragment compression unit is to configure a set of pixels associated with a single cacheline of the render cache to be rendered by the pixel pipeline as a coarse pixel.

5. The graphics processing unit as in claim 4 , wherein the pixel pipeline includes a cache read module to issue a read request to the render cache, the read request to read a coarse pixel quad from the render cache.

6. The graphics processing unit as in claim 5 , wherein the pixel pipeline includes a cache write module to issue a write request to the render cache, the write request to write a coarse pixel quad to the render cache.

7. The graphics processing unit as in claim 6 , wherein the post-shader pixel processing unit is to perform a post-shader pixel processing operation on the coarse pixel.

8. The graphics processing unit as in claim 7 , wherein the post-shader pixel processing operation includes a stencil, depth, or blend operation.

9. The graphics processing unit as in claim 1 , wherein the render cache includes a cache allocation unit to perform cacheline aware fragment expansion of a coarse pixel.

10. The graphics processing unit as in claim 9 , wherein the cache allocation unit is to expand a coarse pixel quad into a pixel quad based on a cache line status associated with the coarse pixel quad.

11. A method of coarse pixel processing on a graphics processing unit, the method comprising:
performing a coarse pixel shading operation on a coarse pixel quad fragment via a parallel processing cluster to generate a coarse pixel quad;
outputting the coarse pixel quad to a post-shader pixel pipeline;
performing coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline;
writing, via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache; and
evicting the processed coarse pixel quad from the render cache as a coarse pixel.

12. The method as in claim 11 , additionally comprising performing cacheline aware fragment compression on a set of pixel quads to process the set of pixel quads as a coarse pixel when the set of pixel quads cover a cacheline of the render cache.

13. The method as in claim 11 , additionally comprising performing cacheline aware fragment expansion on a coarse pixel quad to expand the coarse pixel quad into constituent pixel quads when the coarse pixel quad is not fully lit.

14. The method as in claim 11 , additionally comprising performing cacheline aware fragment expansion on a coarse pixel quad to expand the coarse pixel quad into constituent pixel quads when the coarse pixel quad does not cover a full cacheline of the render cache.

15. The method as in claim 14 , wherein a coarse pixel quad is determined to cover a full cacheline of the render cache based on a size of a cacheline and a coarse pixel scaling factor.

16. A data processing system comprising:
a memory device to store a render target; and
a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel pipeline, a render cache to store coarse pixel data processed by and output from a post-shader pixel processing unit of the pixel pipeline, and a graphics processor cache to store coarse pixel data evicted from the render cache as coarse pixels.

17. The data processing system as in claim 16 , wherein the render cache of the graphics processing unit is additionally to store coarse pixel data for input to the post-shader pixel processing unit.

18. The data processing system as in claim 16 , wherein the processing cluster is configurable to adjust a scale factor of a coarse pixel during the coarse pixel shading.

19. The data processing system as in claim 16 , wherein the pixel pipeline of the graphics processing unit includes a fragment compression unit to implement cacheline aware fragment compression, wherein the fragment compression unit is to configure a set of pixels associated with a single cacheline of the render cache to be rendered by the pixel pipeline as a coarse pixel.

20. The data processing system as in claim 16 , wherein the render cache of the graphics processing unit includes a cache allocation unit to perform cacheline aware fragment expansion of a set of coarse pixels, the cache allocation unit to expand a coarse pixel quad into a pixel quad based on a cache line status associated with the coarse pixel quad.

Assignees

• Intel Corp

Inventors

• Surti Prasoonkumar
• Appu Abhishek R
• Dasgupta Subhajit
• Mysore Srivallaba
• Norris Michael J
• Ranganathan Vasanth
• Ray Joydeep

Classifications

• G06T2210/52

  Parallel processing · CPC title

• G06T15/80 Primary

  Shading · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title