Dynamically updating logical identifiers of cores of a processor

Patent metadata

Field	Value
Publication number	US-10706004-B2
Application number	US-201715811848-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Feb 27, 2015
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
receiving, in a first logic of a processor, environmental information regarding operation of the processor, usage information for a plurality of cores of the processor, and characteristic information for the plurality of cores;
selecting a first core on which one or more threads are executed to be dynamically remapped from association with a first logical identifier to association with a second logical identifier based on at least some of the environmental information, the usage information, and the characteristic information; and
causing the first core to enter into a low power state, and associating the second logical identifier with the first core, to cause the one or more threads to be dynamically migrated to a second core to be associated with the first logical identifier, wherein in response to an abort signal from the first core, preventing the first core from entering into the low power state and not associating the second logical identifier with the first core.

2. The machine-readable medium of claim 1 , wherein the method further comprises issuing a remap signal to the first core and at least a portion of uncore circuitry of the processor, to cause the first core and at least the portion of the uncore circuitry to be quiesced, prior to causing the first core to enter into the low power state.

3. The machine-readable medium of claim 1 , wherein the method further comprises causing the second core to exit a low power state and providing the first logical identifier to the second core for storage in a logical identifier storage of the second core.

4. The machine-readable medium of claim 3 , wherein the method further comprises, after the first logical identifier is stored in the logical identifier storage of the second core, accessing context information of the one or more threads from a shared cache memory, and resuming execution of the one or more threads on the second core.

5. The machine-readable medium of claim 1 , wherein the method further comprises:
selecting the first core when power characteristic information associated with the first core is higher than power characteristic information associated with the second core and a subset of the plurality of cores are active; and
causing the first core to enter a low power state after the dynamic remap.

6. The machine-readable medium of claim 1 , wherein the method further comprises selecting the first core when the second core is to operate at a higher turbo mode frequency than the first core, wherein the one or more threads comprise high priority threads.

7. The machine-readable medium of claim 1 , wherein the method further comprises selecting the first core when a temperature of the first core exceeds a thermal threshold, and a temperature of the second core is less than the thermal threshold.

8. The machine-readable medium of claim 1 , wherein the method further comprises selecting the first core after a threshold time, to enable wear leveling of the plurality of cores.

9. A system comprising:
a processor having:
a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core;
a power controller, based at least in part on a temperature associated with a first core, to dynamically remap a first logical identifier from association with the first core to association with a second core while the first core and the second core are in a low power state, to cause a first thread in execution on the first core to be migrated from the first core to the second core transparently to an operating system;
a first mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association for a core;
an input/output (I/O) interface to couple to one or more devices and to provide an incoming message to a selected core; and
a second mapping table coupled to the I/O interface including a second plurality of entries each to store a logical identifier-to-physical identifier association for a core, wherein the power controller is to dynamically update a first entry of the first mapping table to associate the first logical identifier with the second core and cause a dynamic update to a corresponding entry of the second mapping table to associate the first logical identifier with the second core; and

a system memory coupled to the processor, wherein the system memory comprises a non-volatile storage.

10. The system of claim 9 , wherein the processor further comprises a storage to store a plurality of entries each associated with a core and including a plurality of characterization values for the core, wherein at least some of the plurality of cores have a different characterization value for a first operating parameter, based on manufacturing variation.

11. The system of claim 9 , wherein the power controller is to cause the second core to exit the low power state and thereafter provide the first logical identifier to the second core for storage in the second storage of the second core.

12. The system of claim 11 , wherein the second core is to access context information of the first thread from a shared cache memory and resume execution of the first thread, based at least in part on the first logical identifier.

13. A processor comprising:
a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage separate from the first storage to store a logical identifier associated with the core, the physical identifier for the core not visible to an operating system;
a plurality of thermal sensors to measure a temperature at a corresponding location of the processor;
a plurality of power sensors to measure a power at a corresponding location of the processor;
a plurality of wear sensors to measure wear information regarding the plurality of cores;
a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on at least one of a temperature and a power associated with the first core, the dynamic remapping to cause a first thread in execution on the first core to be migrated from the first core to the second core; and
a mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the dynamic core identifier logic is to update an entry of the mapping table associated with the second core in response to the dynamic remapping of the first logical identifier to the second core to store the first logical identifier in the entry associated with the second core.

14. The processor of claim 13 , further comprising an input/output (I/O) interface coupled to the plurality of cores, wherein the I/O interface is associated with a second mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the dynamic core identifier logic is to communicate the update to the entry of the mapping table to the I/O interface to enable the second mapping table to be updated.

15. The processor of claim 13 , further comprising a first storage to store usage history information regarding usage of the plurality of cores.

16. Th

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Sistla Krishnakanth V
• Sotomayor Guy G
• Henroid Andrew D
• Gough Robert E
• Schiff Tod F

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title