Logic switching device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10702940-B2
Application number	US-201916391477-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Aug 20, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.

First claim

What is claimed is:

1. A logic switching device comprising:
a channel;
a source and a drain both connected to the channel;
a gate electrode arranged to face the channel; and
a domain switching layer between the channel and the gate electrode,
wherein the domain switching layer is a non-memory element, has a non-hysteretic behavior characteristic at a polarization change according to an external electric field, and comprises at least one structure including at least one ferroelectric material region comprising a ferroelectric domain and at least one anti-ferroelectric material region comprising an anti-ferroelectric domain.

2. The logic switching device of claim 1 , wherein the domain switching layer comprises the at least one ferroelectric material region and the at least one anti-ferroelectric material region are arranged in a direction parallel to the gate electrode.

3. The logic switching device of claim 1 , wherein the domain switching layer comprises the at least one ferroelectric material region and the at least one anti-ferroelectric material region are arranged in a direction perpendicular to the gate electrode.

4. The logic switching device of claim 1 , wherein the domain switching layer comprises two structures, a first structure including the at least one ferroelectric material region and the at least one anti-ferroelectric material region are arranged in a direction parallel to the gate electrode and a second structure including at least one ferroelectric material region and at least one anti-ferroelectric material region are arranged in a direction perpendicular to the gate electrode.

5. The logic switching device of claim 1 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprise an identical base material, but have different crystalline phases.

6. The logic switching device of claim 1 , wherein the at least one ferroelectric material region has an orthorhombic crystalline phase, and the at least one anti-ferroelectric material region has a tetragonal crystalline phase.

7. The logic switching device of claim 1 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region have different doping concentrations.

8. The logic switching device of claim 1 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprise different dopants.

9. The logic switching device of claim 1 , wherein at least one of the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprises at least one of a Hf-based oxide or a Zr-based oxide.

10. The logic switching device of claim 1 , wherein at least one of the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprises a dopant, wherein the dopant comprises at least one of silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), strontium (Sr), and hafnium (Hf).

11. The logic switching device of claim 1 , wherein a volume ratio of the at least one ferroelectric material region to the at least one anti-ferroelectric material region in the domain switching layers is in a range from about 10:90 to about 90:10.

12. The logic switching device of claim 1 , wherein the domain switching layer is in direct contact with the channel.

13. The logic switching device of claim 1 , further comprising:
an insulating layer between the channel and the domain switching layer.

14. The logic switching device of claim 1 , further comprising:
an insulating layer between the channel and the domain switching layer; and
a conductive layer between the insulating layer and the domain switching layer.

15. The logic switching device of claim 1 , wherein the channel comprises at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), a Group III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, a quantum dot, and an organic semiconductor.

16. A method of manufacturing a logic switching device, the method comprising:
preparing a substrate comprising a channel;
forming an amorphous thin film on the channel;
forming a conductive material layer on the amorphous thin film; and
annealing the amorphous thin film to form a domain switching layer from the amorphous thin film,
wherein the domain switching layer is a non-memory element, has a non-hysteretic behavior characteristic at a polarization change according to an external electric field, and comprises at least one ferroelectric material region comprising a ferroelectric domain and at least one anti-ferroelectric material region comprising an anti-ferroelectric domain.

17. The method of claim 16 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region have different crystalline phases.

18. The method of claim 16 , wherein the at least one ferroelectric material region has an orthorhombic crystalline phase, and the at least one anti-ferroelectric material region has a tetragonal crystalline phase.

19. The method of claim 16 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region have different doping concentrations.

20. The method of claim 16 , wherein the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprise different dopants.

21. The method of claim 16 , wherein at least one of the at least one ferroelectric material region and the at least one anti-ferroelectric material region comprises at least one of a Hf-based oxide or a Zr-based oxide.

22. The method of claim 16 , wherein the annealing is performed at a temperature in the range from about 400° C. to about 1200° C.

23. The method of claim 16 , further comprising:
forming a gate electrode from the conductive material layer.

24. The method of claim 16 , further comprising:
forming a source and a drain both connected to the channel.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Heo Jinseong
• Lee Yunseong
• Jo Sanghyun

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/683

  being parallel to the channel plane · CPC title