Annealed seed layer for magnetic random access memory

Patent metadata

Field	Value
Publication number	US-10700263-B2
Application number	US-201815886232-A
Country	US
Kind code	B2
Filing date	Feb 1, 2018
Priority date	Feb 1, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a trench within a substrate;
forming a liner in contact with a bottom surface and sidewalls of the trench;
forming a trench line within the trench and in contact with the liner;
forming a pad layer above the trench line and in contact with a respective top surface of each of the substrate, the liner, and the trench line;
forming a seed layer on and in contact with the pad layer;
annealing the seed layer, wherein the annealing alters a grain structure of the seed layer and roughens a top surface of the seed layer;
planarizing the seed layer after the seed layer has been annealed, wherein the planarizing smooths the top surface of the seed layer; and
forming a magnetic tunnel junction stack on and in contact with the seed layer after the seed layer has been planarized.

2. The method of claim 1 , wherein the annealing is performed at a temperature ranging from 200° C. to 400° C.

3. The method of claim 1 , wherein the seed layer is planarized to have a Root Mean Square surface roughness ranging from 1 Angstrom to 3 Angstroms.

4. The method of claim 1 , wherein forming the magnetic tunnel junction stack comprises:
depositing magnetic tunnel junction stack layers on and in contact with the seed layer; and
etching the magnetic tunnel junction stack layers to form the magnetic tunnel junction stack.

5. The method of claim 4 , wherein etching the magnetic tunnel junction stack layers to form the magnetic tunnel junction stack comprises:
forming a hardmask on the magnetic tunnel junction stack layers; and
etching portions of the magnetic tunnel junction stack layers not underlying the hardmask.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Kothandaraman Chandrasekharan
• Nowak Janusz J
• O'Sullivan Eugene J

Classifications

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/80 Primary

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H01L43/02 Primary

  Electricity · mapped topic