Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10700206-B2
Application number	US-201816207067-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Nov 30, 2015
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked in a first direction;
forming an isolation insulating layer over the fin structure;
forming anchor regions by patterning the isolation insulating layer, thereby partially exposing the fin structure, end portions of the fin structure being buried in the anchor regions;
at least partially removing the second semiconductor layers in the partially exposed fin structure;
forming dummy gate structures with sidewall spacers;
partially removing the sidewall spacers from source/drain regions of the fin structure to partially expose the fin structure in the source/drain regions;
forming epitaxial source/drain structures on the partially exposed fin structure in the source/drain regions; and
forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in a channel region,
wherein, after the gate electrode layer is formed, a bottom of the source/drain regions of the fin structure are covered by the sidewall spacers.

2. The method of claim 1 , wherein after the gate electrode layer is formed, the first semiconductor layers and the second semiconductor layers are alternately stacked at the anchor regions, and no gate electrode layer and no gate dielectric are included in the anchor regions.

3. The method of claim 2 , wherein:
the first semiconductor layers are made of Si, and
the second semiconductor layers are made of SiGe.

4. The method of claim 2 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

5. The method of claim 2 , wherein the epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

6. The method of claim 2 , wherein the epitaxial source/drain structures include SiGe.

7. The method of claim 1 , wherein the second semiconductor layers are only partially removed in the partially exposed fin structure.

8. The method of claim 7 , wherein the epitaxial source/drain structures cover the first semiconductor layers and the second semiconductor layers in the source/drain regions.

9. A semiconductor device, comprising:
first channel layers and a second channel layer disposed over a substrate;
a first source/drain region and a second source/drain region disposed over the substrate;
a first source/drain epitaxial layer covering an upper portion of the first source/drain region, and a second source/drain epitaxial layer covering an upper portion of the second source/drain region;
a first gate dielectric layer disposed on each of the first channel layers and a second gate dielectric layer disposed on the second channel layer;
a gate electrode layer disposed on the first gate dielectric layer and the second gate dielectric layer; and
sidewall spacers disposed on opposing side faces of the gate electrode layer, wherein:
each of the first channel layers includes a semiconductor wire made of a first semiconductor material,
the semiconductor wire passes through the first source/drain region and enters into an anchor region, and
a bottom portion of the first source/drain region and a bottom portion of the second source/drain region are covered by an insulating layer made of a same material as the sidewall spacers.

10. The semiconductor device of claim 9 , wherein at the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric layer, and is sandwiched by a second semiconductor material different from the first semiconductor material.

11. The semiconductor device of claim 10 , wherein:
the first semiconductor material is made of SiGe, and
the second semiconductor material is Si.

12. The semiconductor device of claim 10 , wherein:
the second channel layer includes a stacked structure of the first semiconductor material and the second semiconductor material.

13. The semiconductor device of claim 12 , wherein:
the first semiconductor material is made of Si, and
the second semiconductor material is made of SiGe.

14. The semiconductor device of claim 10 , wherein at the anchor region, the second channel layer has no gate electrode layer and no gate dielectric layer.

15. A semiconductor device, comprising:
a fin structure having a channel layer, source/drain regions and anchored regions;
source/drain epitaxial regions covering an upper portion of the source/drain regions;
a gate dielectric layer disposed on the channel layer;
a gate electrode layer disposed on the gate dielectric layer; and
sidewall spacers disposed on opposing side faces of the gate electrode layer, wherein:
the anchored regions are embedded in anchor regions,
the channel layer includes first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction,
widths of the first semiconductor layers in the channel layer are smaller than widths of the second semiconductor layers in the channel layer,
the widths of the first semiconductor layers in the channel layer are smaller than widths of the first semiconductor layers in the anchor region, and
a bottom portion of the source/drain region is covered by an insulating layer made of a same material as the sidewall spacers.

16. The semiconductor device of claim 15 , wherein at the anchor region, the fin structure has no gate electrode layer and no gate dielectric layer.

17. The semiconductor device of claim 16 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

18. The semiconductor device of claim 17 , wherein:
the first semiconductor layers are made of Si, and
the second semiconductor layers are made of SiGe.

19. The semiconductor device of claim 16 , wherein the source/drain epitaxial regions include at least one of SiP, SiCP and SiC.

20. The semiconductor device of claim 16 , wherein the source/drain epitaxial regions include SiGe.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen I-Sheng
• Yeh Chih Chieh
• Wu Cheng-Hsien

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title