SMD package with flat contacts to prevent bottleneck

Patent metadata

Field	Value
Publication number	US-10699987-B2
Application number	US-201815954233-A
Country	US
Kind code	B2
Filing date	Apr 16, 2018
Priority date	Apr 18, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

First claim

What is claimed is:

1. A package enclosing a power semiconductor die, the package having a package top side and a package footprint side, the die having a first load terminal at a die frontside facing the package footprint side and a second load terminal arranged at a die backside facing the package top side, wherein the package comprises:
a lead frame configured to electrically and mechanically couple the package to a support, the lead frame having a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal,
wherein at least one of:
the planar first outside terminal is configured to interface with the support by means of a first contact area and the planar second outside terminal is configured to interface with the support by means of a second contact area having a size that is within a range between 80% and 120% of a size of the first contact area; and
the first outside terminal has a first current rating and the second outside terminal has a second current rating that is within a range between 80% and 120% of the first current rating, and

wherein the power semiconductor die is configured to conduct a load current between the first load terminal and the second load terminal in a range between 1 A and 300 A, and block a voltage between the first load terminal and the second load terminal in a range between 10 V and 500 V.

2. The package of claim 1 , wherein the package is a surface-mount package.

3. The package of claim 1 , wherein the die has a power semiconductor transistor configuration, wherein the first load terminal is a source terminal, and wherein the second load terminal is a drain terminal.

4. The package of claim 1 , wherein each of the first contact area and the second contact area is formed by a respective contiguous area.

5. The package of claim 1 , wherein the electrical connection between the second outside terminal and the second load terminal comprises a clip that is disposed over the die backside and extends over and spaced from an edge of the die to the second outside terminal.

6. The package of claim 1 , wherein each of the first contact area and the second contact area laterally overlap with the die at least partially.

7. The package of claim 6 , wherein at least 50% of the first contact area laterally overlaps with the die and/or at least 10% of the second contact area laterally overlaps with the die.

8. The package of claim 1 , wherein the first outside terminal is configured with the first current rating and the second outside terminal is configured with the second current rating, the second current rating is in the range between 80% and 120% of the first current rating.

9. The package of claim 1 , wherein the first current rating is at least 20 A/mm2.

10. The package of claim 1 , wherein the size of the second contact area is in a range between 80% and 120% of the size of the first contact area.

11. The package of claim 1 , wherein the electrical connection between the first load terminal and the first outside terminal and the electrical connection between the second load terminal and the second outside terminal are free of any bond wires and free of any ribbons.

12. The package of claim 1 , wherein the first contact area and the second contact area are arranged symmetrically to each other.

13. The package of claim 1 , wherein the die has a further terminal at the die frontside, wherein the lead frame has a planar third outside terminal electrically connected with the further terminal and electrically insulated from each of the first outside terminal and the second outside terminal, and wherein the planar third outside terminal is configured to interface with the support by means of a third contact area.

14. The package of claim 13 , wherein the third contact area has a size that is within a range between 80% and 120% of the size of the first contact area.

15. The package of claim 1 , wherein the lead frame is configured to couple the package to the support such that the package footprint side faces a surface of the support.

16. The package of claim 1 , wherein the package has a footprint area, and wherein each of the first contact area and the second area has a size within 10% to 30% of a size of the footprint area.

17. A package, comprising:
a lead frame comprising a first outside terminal and a second outside terminal; and
a power semiconductor die at partly enclosed in an insulating material and comprising a first load terminal facing and electrically connected to the first outside terminal and a second load terminal at an opposite side of the die as the first load terminal and electrically connected to the second outside terminal,
wherein the first outside terminal has a planar first contact area facing away from the die and configured for surface mounting to a support,
wherein the second outside terminal has a planar second contact area facing away from the die and configured for surface mounting to the support,
wherein the package has a footprint area which includes the planar first contact area and the planar second contact area,
wherein the planar first contact area and the planar second contact area are each smaller than 30% of the footprint area.

18. The package of claim 17 , wherein the planar first contact area and the planar second contact area are of substantially equal size.

19. A method of producing a package for enclosing a power semiconductor die, the package having a package top side and a package footprint side, the die having a first load terminal at a die frontside facing the package footprint side and a second load terminal arranged at a die backside facing the package top side, the method comprising:
providing a lead frame configured to electrically and mechanically couple the package to a support, the lead frame having a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, wherein the planar first outside terminal is configured to interface with the support by means of a first contact area, and the planar second outside terminal is configured to interface with the support by means of a second contact area; and
configuring the second contact area to have a size that is in a range between 80% and 120% of a size of the first contact area and/or configuring the first outside terminal to have a first current rating and the second outside terminal to have a second current rating that is in a range between 80% and 120% of the first current rating,
wherein the power semiconductor die is configured to conduct a load current between the first load terminal and the second load terminal in a range between 1 A and 300 A, and block a voltage between the first load terminal and the second load terminal in a range between 10 V and 500 V.

Assignees

• Infineon Technologies Austria Ag
• Tinfineon Tech Austria Ag

Inventors

• Otremba Ralf
• Chong Chooi Mei
• Dinkel Markus
• Hoeglauer Josef
• Schiess Klaus
• Schloegel Xaver

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/424

  Cross-sectional shapes (H10W70/481 takes precedence) · CPC title

• H10W70/481 Primary

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/466

  Tape carriers or flat leads · CPC title

• H10W70/041

  Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps · CPC title