Electronic device

Patent metadata

Field	Value
Publication number	US-10699794-B2
Application number	US-201816199603-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	May 21, 2015
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

First claim

What is claimed is:

1. A neural network comprising:
an artificial neuron comprising a first transistor and a capacitor;
a first line;
a second line; and
an input circuit configured to supply potential corresponding to an input value of the artificial neuron,
wherein a gate of the first transistor is electrically connected to the first line,
wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,
wherein a second terminal of the capacitor is electrically connected to the input circuit via the second line, and
wherein a channel formation region of the first transistor comprises an oxide semiconductor.

2. The neural network according to claim 1 , further comprising:
a circuit comprising a second transistor,
wherein a channel formation region of the second transistor comprises silicon.

3. The neural network according to claim 1 ,
wherein the first transistor is provided over a silicon substrate.

4. A neural network comprising:
artificial neurons each comprising a transistor and a capacitor;
an input circuit configured to supply potential corresponding to input values of the artificial neurons,
wherein a first terminal of the transistor is electrically connected to a first terminal of the capacitor,
wherein a second terminal of the capacitor is electrically connected to the input circuit via the second line,
wherein a channel formation region of the transistor comprises an oxide semiconductor, and
wherein the transistors are configured to control weakening of bonds between synapses of the neural network.

5. The neural network according to claim 4 ,
wherein the transistors are provided over a silicon substrate.

6. The neural network according to claim 4 ,
wherein in each of the artificial neurons, the transistor is configured to hold a potential of the node.

7. A neural network comprising:
artificial neurons each comprising a first transistor and a capacitor; and
a first circuit configured to perform calculation using outputs of the artificial neurons,
an input circuit configured to supply potential corresponding to input values of the artificial neurons,
wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,
wherein a second terminal of the capacitor is electrically connected to the input circuit, and
wherein a channel formation region of the first transistor comprises an oxide semiconductor.

8. The neural network according to claim 7 ,
wherein the first transistors are provided over a silicon substrate.

9. The neural network according to claim 7 , further comprising:
a second circuit comprising a second transistor,
wherein a channel formation region of the second transistor comprises silicon.

Assignees

• Semiconductor Energy Lab

Inventors

• Ikeda Takayuki
• Kurokawa Yoshiyuki

Classifications

• G06N3/065

  Analogue means · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title