Memory device with a driving circuit comprising transistors each having two gate electrodes and an oxide semiconductor layer

Patent metadata

Field	Value
Publication number	US-10297322-B2
Application number	US-201615219773-A
Country	US
Kind code	B2
Filing date	Jul 26, 2016
Priority date	Aug 27, 2010
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

First claim

The invention claimed is:

1. An electronic device comprising:
a driving circuit comprising a first transistor and a first capacitor; and
a memory cell array circuit comprising a second transistor and a memory element,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, a first gate electrode, a source electrode and a drain electrode,
wherein the second transistor comprises a gate insulating film between the oxide semiconductor layer and the first gate electrode,
wherein the first capacitor comprises a first electrode and a second electrode,
wherein the memory element is electrically connected to one of the source electrode and the drain electrode of the second transistor,
wherein the source electrode and the drain electrode of the first transistor are electrically connected to the oxide semiconductor layer of the first transistor,
wherein the source electrode and the drain electrode of the second transistor are electrically connected to the oxide semiconductor layer of the second transistor,
wherein the first gate electrode and one of the source electrode and the drain electrode of the first transistor are electrically connected to the first electrode of the first capacitor,
wherein a constant electrical potential is supplied to the other of the source electrode and the drain electrode of the first transistor, and
wherein an electrical potential of the first gate electrode of the second transistor is substantially equal to an electrical potential of the first electrode of the first capacitor at any time.

2. The electronic device according to claim 1 ,
wherein the memory element is a second capacitor.

3. The electronic device according to claim 1 ,
wherein the memory element comprises a third transistor,
wherein the third transistor comprises a gate electrode, and
wherein the one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the third transistor.

4. The electronic device according to claim 1 ,
wherein the first transistor comprises a second gate electrode,
wherein the second transistor comprises a second gate electrode, and
wherein the second gate electrode of the first transistor is electrically connected to the first electrode of the first capacitor.

5. The electronic device according to claim 4 ,
wherein a potential of the first electrode of the first capacitor is configured to be always lower than the lowest potential of the second gate electrode of the second transistor.

6. The electronic device according to claim 4 ,
wherein the oxide semiconductor layer of the first transistor is interposed between the first gate electrode and the second gate electrode of the first transistor, and
wherein the oxide semiconductor layer of the second transistor is interposed between the first gate electrode and the second gate electrode of the second transistor.

7. An electronic device comprising:
a driving circuit comprising a first transistor and a first capacitor; and
a memory cell comprising a second transistor and a memory element,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, a first gate electrode, a source electrode and a drain electrode,
wherein the second transistor comprises a gate insulating film between the oxide semiconductor layer and the first gate electrode,
wherein the first capacitor comprises a first electrode and a second electrode,
wherein the memory element is electrically connected to one of the source electrode and the drain electrode of the second transistor,
wherein the source electrode and the drain electrode of the first transistor are electrically connected to the oxide semiconductor layer of the first transistor,
wherein the source electrode and the drain electrode of the second transistor are electrically connected to the oxide semiconductor layer of the second transistor,
wherein the first gate electrode and one of the source electrode and the drain electrode of the first transistor are electrically connected to the first electrode of the first capacitor,
wherein a constant electrical potential is supplied to the other of the source electrode and the drain electrode of the first transistor, and
wherein an electrical potential of the first gate electrode of the second transistor is substantially equal to an electrical potential of the first electrode of the first capacitor at any time.

8. The electronic device according to claim 7 ,
wherein the memory element is a second capacitor.

9. The electronic device according to claim 7 ,
wherein the memory element comprises a third transistor,
wherein the third transistor comprises a gate electrode, and
wherein the one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the third transistor.

10. The electronic device according to claim 7 ,
wherein the first transistor comprises a second gate electrode,
wherein the second transistor comprises a second gate electrode, and
wherein the second gate electrode of the first transistor is electrically connected to the first electrode of the first capacitor.

11. The electronic device according to claim 10 ,
wherein a potential of the first electrode of the first capacitor is configured to be always lower than the lowest potential of the second gate electrode of the second transistor.

12. The electronic device according to claim 10 ,
wherein the oxide semiconductor layer of the first transistor is interposed between the first gate electrode and the second gate electrode of the first transistor, and
wherein the oxide semiconductor layer of the second transistor is interposed between the first gate electrode and the second gate electrode of the second transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun

Classifications

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/02

  electrically programmable · CPC title

• G11C11/403 Primary

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title