Silicon interposer, semiconductor package using the same, and fabrication method thereof
US-9748167-B1 · Aug 29, 2017 · US
US10698156B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10698156-B2 |
| Application number | US-201815891847-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 8, 2018 |
| Priority date | Apr 27, 2017 |
| Publication date | Jun 30, 2020 |
| Grant date | Jun 30, 2020 |
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There is set forth herein a method including building an interposer base structure on a first wafer having a first substrate, wherein the building an interposer base structure includes fabricating a plurality of through vias that extend through the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layer; building a photonics structure on a second wafer having a second substrate, wherein the building a photonics structure includes fabricating within a photonics device dielectric stack formed on the second substrate one or more photonics device; and bonding the photonics structure to the interposer base structure to define an interposer having the interposer base structure and one or more photonics device fabricated within the photonics device dielectric stack. There is set forth herein an optoelectrical system including a substrate; an interposer dielectric stack formed on the substrate, the interposer dielectric stack including a base interposer dielectric stack, and a photonics device dielectric stack, and a bond layer dielectric stack that integrally bonds the photonics device dielectric stack to the base interposer dielectric stack.
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What is claimed is: 1. A method comprising: building an interposer base structure on a first wafer having a first substrate, wherein the building an interposer base structure includes fabricating a plurality of through vias that extend through the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layer; building a photonics structure on a second wafer having a second substrate, wherein the building a photonics structure includes fabricating within a photonics device dielectric stack formed on the second substrate one or more photonics device; and bonding the photonics structure to the interposer base structure to define an interposer having the interposer base structure and one or more photonics device fabricated within the photonics device dielectric stack, wherein the bonding defines a bond layer between the base interposer dielectric stack and the photonics device dielectric stack, wherein the method is performed so that a through via of the plurality of through vias is connected to an associated vertically extending photonics structure through via, and wherein the method is performed so that the vertically extending photonics structure through via extends through the photonics device dielectric stack and the bond layer. 2. The method of claim 1 , wherein the bonding includes using a low temperature oxide bond process. 3. The method of claim 1 , wherein the bonding includes using a low temperature oxide fusion bond process that includes a polishing stage, an activation stage and an anneal stage. 4. The method of claim 1 , wherein the second wafer is a silicon on insulator (SOI) wafer. 5. The method of claim 1 , wherein the method includes subsequent to the bonding removing material from the first substrate to reveal through vias of the plurality of through vias so that the through vias extend entirely through the first substrate. 6. The method of claim 1 , wherein the fabricating a plurality of through vias that extend through the first substrate includes performing the fabricating so that though vias of the plurality of through vias to extend to such depth within the first substrate so that the through vias extend entirely through the first substrate on performing removal of material of the first substrate to reveal the plurality of through vias. 7. The method of claim 1 , wherein the method includes forming a plurality of photonics structure through vias through the photonics device dielectric stack. 8. The method of claim 1 , wherein the method includes forming a plurality of photonics structure through vias through the photonics device dielectric stack, and connecting photonics structure through vias of the plurality of photonics structure through vias to through vias of the plurality of through vias using respective bridge connections, the respective bridge connections having features defined within the interposer base dielectric stack. 9. The method of claim 1 , wherein the building a photonics structure on a second wafer includes fabricating within a photonics device dielectric stack a first waveguide of a first material and a second waveguide of a second material, wherein the building a photonics structure on a second wafer includes fabricating within a photonics device dielectric stack the first waveguide at a first elevation, and the second waveguide at a second elevation, and wherein the building a photonics structure on a second wafer includes fabricating within the photonics device dielectric stack a photodetector including light sensitive material. 10. The method of claim 1 , wherein the method includes forming a conductive path having a redistribution layer connected to the through via of the plurality of through vias extending through the first substrate, which through via is connected to the associated vertically extending photonics structure through via, wherein the method is performed so that the vertically extending photonics structure through via extends through the photonics device dielectric stack, wherein the method includes forming the base interposer dielectric on a frontside of the first substrate, and forming the redistribution layer on a backside of the first substrate. 11. The method of claim 1 , wherein the method includes forming a conductive path providing a connection, the connection defined by a conductive path including a redistribution layer connected to the through via of the plurality of through vias extending through the first substrate, which through via is connected to the associated vertically extending photonics structure through via extending through the photonic device dielectric stack, wherein the method is performed so that the vertically extending photonics structure through via is connected to a first metallization layer, which first metallization layer is connected to a second vertically extending photonics structure through via, which second vertically extending photonics structure through via is connected to a second metallization layer, wherein the second metallization layer is at a lower elevation than the first metallization layer. 12. The method of claim 1 , wherein the method includes forming a conductive path having a redistribution layer connected to the through via of the plurality of through vias extending through the first substrate, which through via is connected by a bridge connection to the associated vertically extending photonics structure through via, wherein the method includes forming the base interposer dielectric stack on a frontside of the first substrate, wherein the method includes forming the redistribution layer on a backside of the first substrate, wherein the bridge connection includes features formed in the base interposer dielectric stack. 13. The method of claim 1 , wherein the method includes forming a conductive path having a redistribution layer connected to the through via of the plurality of through vias extending through the first substrate, which through via is connected by a bridge connection to the associated vertically extending photonics structure through via, wherein the base interposer dielectric stack is formed on a frontside of the first substrate, wherein the redistribution layer is formed on a backside of the first substrate, wherein the bridge connection includes features formed in the base interposer dielectric stack, wherein the method includes forming the bridge connection to include a first metallization layer formed in the base interposer dielectric stack connected to the through via of the plurality of through vias, a contact via formed in the base interposer dielectric stack connected to the first metallization layer, a second metallization formed in the base interposer dielectric stack connected to the contact via, which second metallization layer is connected to the associated vertically extending photonics structure through via. 14. The method of claim 1 , wherein the bonding the photonics structure to the interposer base structure includes performing the bonding to define the bond layer between the base interposer dielectric stack and the photonics device dielectric stack, wherein the method includes forming a conductive path having a redistribution layer connected to the through via of the plurality of through vias extending through the first substrate, which through via is connected by a bridge connection to the associated vertically extending photonics structure through via, wherein the vertically extending photonics structure through via extends through the bond layer that connects the base interposer dielectric stack and the photonics device dielectric stack, whe
Subject matter not provided for in other groups of this subclass · CPC title
comprising use of blind vias during the manufacture · CPC title
comprising etching via holes that stop on pads or on electrodes · CPC title
in silicon-on-insulator [SOI] wafers · CPC title
comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title
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