Testing of semiconductor devices and devices, and designs thereof

Patent metadata

Field	Value
Publication number	US-10698022-B2
Application number	US-201815950972-A
Country	US
Kind code	B2
Filing date	Apr 11, 2018
Priority date	Dec 19, 2013
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a reconstituted wafer comprising a plurality of semiconductor chips having a plurality of contact pads;
forming a passivation layer over the reconstituted wafer;
forming a plurality of openings in the passivation layer to expose the plurality of contact pads; and
forming a first redistribution metal line, a second redistribution metal line, a shield redistribution line, and contact pads by electroplating a fill metal, wherein the first redistribution metal line and the second redistribution metal line are metal lines configured to supply different voltages to the plurality of semiconductor chips, and wherein the shield redistribution metal line is not coupled to any functional circuit in any of the plurality of semiconductor chips in the reconstituted wafer, and wherein the shield redistribution metal line is configured to be isolated from all internal nodes of the plurality of semiconductor chips in the reconstituted wafer.

2. The method of claim 1 , wherein the shield redistribution metal lines do not extend into opening in the passivation layer.

3. The method of claim 1 , wherein the shield redistribution metal line is not coupled to any functional circuit in any of the plurality of semiconductor chips in the reconstituted wafer.

4. The method of claim 1 , further comprising forming exposed pads, wherein a stress voltage is configured to be applied to the shield redistribution metal lines through the exposed pads.

5. The method of claim 1 , wherein forming a first redistribution metal line, a second redistribution metal line, a shield redistribution line, and contact pads further comprises:
forming the first redistribution metal line, the second redistribution metal line, and the shield redistribution line in the same metal level.

6. The method of claim 1 , wherein forming a first redistribution metal line, a second redistribution metal line, a shield redistribution line, and contact pads further comprises:
forming the first redistribution metal line, the second redistribution metal line, and the shield redistribution line in different metal levels.

7. The method of claim 1 , further comprising a third redistribution line disposed over the shield redistribution line, wherein a stress voltage is configured to be applied to the shield redistribution metal lines through the third redistribution line.

8. The method of claim 1 , wherein forming a first redistribution metal line, a second redistribution metal line, a shield redistribution line, and contact pads further comprises:
forming a seed layer over the plurality of openings and the passivation layer;
forming a patterned photo resist layer over the seed layer;
electroplating the fill metal between the patterned photo resist layer;
removing the patterned photo resist layer to expose the underlying portion of the seed layer; and
removing the exposed seed layer.

9. The method of claim 1 , wherein the fill metal comprises copper.

10. A method of fabricating a semiconductor device, the method comprising:
providing a substrate comprising a semiconductor chip having circuitry embedded in an encapsulant;
forming a first redistribution metal line over the semiconductor chip;
forming a second redistribution metal line adjacent the first redistribution metal line, wherein the first redistribution metal line and the second redistribution metal line are metal lines configured to supply different voltages to the circuitry; and
forming a third redistribution metal line between the first redistribution metal line and the second redistribution metal line, the third redistribution metal line not being part of any functional circuit in the substrate and not coupled to any potential node in the substrate, wherein the third redistribution metal line is configured to be isolated from all internal potentials; and
forming an exposed pad, wherein the third redistribution metal line is coupled to the exposed pad.

11. The method of claim 10 , wherein the third redistribution metal line comprises a different material than the first redistribution metal line.

12. The method of claim 10 , wherein the first redistribution metal line comprises copper.

13. The method of claim 12 , wherein the third redistribution metal line comprises a metal nitride.

14. The method of claim 10 , wherein the first redistribution metal line is configured to supply a high voltage to the circuitry in the substrate during operation, wherein the second redistribution metal line is configured to supply a low voltage to the circuitry in the substrate during operation.

15. The method of claim 10 , wherein the first redistribution metal line, the second redistribution metal line, and the third redistribution metal line are formed in the same metal level.

16. The method of claim 10 , wherein the first redistribution metal line, the second redistribution metal line, and the third redistribution metal line are each formed in a different metal level.

17. The method of claim 10 , further comprising forming a fourth redistribution metal line adjacent the first redistribution metal line, wherein the fourth redistribution metal line is in a different metal level than the third redistribution metal line, and wherein the fourth redistribution metal line is coupled to the third redistribution metal line.

18. The method of claim 10 , further comprising forming a first via under the first redistribution metal line, forming a second via under the second redistribution metal line, and forming a third via disposed under the third redistribution metal line.

19. A method comprising:
identifying a region in a layout of a semiconductor device, the region comprising a first metal line configured to be coupled to a high voltage node and a second metal line configured to be coupled to a low voltage node; and
modifying the layout of the semiconductor to include a third metal line between the first metal line and the second metal line, the third metal line having an external contact pad but not being part of, and not coupled to, any functional circuit of the semiconductor device;
providing a substrate comprising a semiconductor chip having circuitry embedded in an encapsulant;
forming a first redistribution metal line over the semiconductor chip;
forming a second redistribution metal line adjacent the first redistribution metal line, wherein the first redistribution metal line and the second redistribution metal line are metal lines configured to supply different voltages to the circuitry;
forming a third redistribution metal line between the first redistribution metal line and the second redistribution metal line, the third redistribution metal line not being part of any functional circuit in the substrate and not coupled to any potential node in the substrate, wherein the third redistribution metal line is configured to be isolated from all internal potentials; and
forming an exposed pad, wherein the third redistribution metal line is coupled to the exposed pad.

20. The method of claim 19 , wherein the ratio of the potential applied during operation to the high voltage node and the potential applied during operation to the low voltage node is 5:1 to 100:1.

21. The method of claim 19 , wherein the distance between the first metal line and the second metal line is a minimum inter-metal distance for the process technology, wherein the distance between the first metal line and the third metal line is less

Assignees

• Infineon Technologies Ag

Inventors

• Roehner Michael
• Aresu Stefano

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title