Semiconductor device, electronic component, and electronic device

Patent metadata

Field	Value
Publication number	US-10693448-B2
Application number	US-201916362777-A
Country	US
Kind code	B2
Filing date	Mar 25, 2019
Priority date	Feb 10, 2016
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

First claim

What is claimed is:

1. An operation method for driving a semiconductor device,
wherein the semiconductor device comprises:
a first transistor comprising a backgate;
a second transistor comprising a backgate;
a third transistor;
a fourth transistor;
a first load comprising a fifth transistor;
a second load comprising a sixth transistor;
a first terminal;
a second terminal;
a third terminal;
a fourth terminal;
a fifth terminal;
a sixth terminal; and
a seventh terminal;

wherein a drain of the third transistor is electrically connected to a source of the first transistor and a source of the second transistor,
wherein a drain of the first transistor is electrically connected to the source of the fifth transistor,
wherein a drain of the second transistor is electrically connected to the source of the sixth transistor,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor is an n-channel transistor,
wherein a drain of the first transistor is electrically connected to the first load,
wherein a drain of the second transistor is electrically connected to the second load,
wherein the first terminal is electrically connected to a gate of the first transistor;
wherein the second terminal is electrically connected to a gate of the second transistor;
wherein the third terminal is electrically connected to a drain of the second transistor;
wherein the fourth terminal is electrically connected to a source of the third transistor;
wherein the fifth terminal is electrically connected to the backgate of the first transistor and the backgate of the second transistor;
wherein one of a drain and a source of the fourth transistor is electrically connected to the second terminal,
wherein the other of the drain and the source of the fourth transistor is electrically connected to the sixth terminal; and
wherein the seventh terminal is electrically connected to a gate of the fourth transistor;
wherein the operation method comprises:
supplying a first potential to the fifth terminal,
supplying a second potential to the sixth terminal,
supplying a third potential to the seventh terminal and resetting the potential of the second terminal,
supplying a fourth potential to the fourth terminal,
supplying a fifth potential to the first terminal and supplying a sixth potential to the second terminal, and
generating a seventh potential based on the comparison of the fifth potential and the sixth potential and supplying the seventh potential to the third terminal.

2. The operation method of the semiconductor device according to claim 1 ,
wherein the second potential is a ground potential.

3. The operation method of the semiconductor device according to claim 2 ,
wherein the fourth potential is a ground potential.

4. The operation method according to claim 1 ,
wherein the first potential is higher than the sixth potential.

5. The operation method of the semiconductor device according to claim 1 ,
wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor comprises a metal oxide layer, a source electrode over and in electrical contact with the metal oxide layer and a drain electrode over and in electrical contact with the metal oxide layer.

6. The operation method of the semiconductor device according to claim 1 ,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor comprises a metal oxide layer, a source electrode over and in electrical contact with the metal oxide layer and a drain electrode over and in electrical contact with the metal oxide layer.

7. An operation method for driving a semiconductor device,
wherein the semiconductor device comprises:
a first transistor comprising a backgate;
a second transistor comprising a backgate;
a third transistor;
a fourth transistor;
a first load;
a second load;
a first terminal;
a second terminal;
a third terminal;
a fourth terminal;
a fifth terminal;
a sixth terminal; and
a seventh terminal;

wherein a drain of the third transistor is electrically connected to a source of the first transistor and a source of the second transistor,
wherein a drain of the first transistor is electrically connected to the first load,
wherein a drain of the second transistor is electrically connected to the second load,
wherein the first terminal is electrically connected to a gate of the first transistor;
wherein the second terminal is electrically connected to a gate of the second transistor;
wherein the third terminal is electrically connected to a drain of the second transistor;
wherein the fourth terminal is electrically connected to a source of the third transistor;
wherein the fifth terminal is electrically connected to the backgate of the first transistor and the backgate of the second transistor;
wherein one of a drain and a source of the fourth transistor is electrically connected to the second terminal,
wherein the other of the drain and the source of the fourth transistor is electrically connected to the sixth terminal; and
wherein the seventh terminal is electrically connected to a gate of the fourth transistor;
wherein the operation method comprises:
supplying a first potential to the fifth terminal,
supplying a second potential to the sixth terminal,
supplying a third potential to the seventh terminal and resetting the potential of the second terminal,
supplying a fourth potential to the fourth terminal,
supplying a fifth potential to the first terminal and supplying a sixth potential to the second terminal,
generating a seventh potential based on the comparison of the fifth potential and the sixth potential and supplying the seventh potential to the third terminal, and
wherein the first potential is higher than the sixth potential.

8. The operation method of the semiconductor device according to claim 7 ,
wherein the second potential is a ground potential.

9. The operation method of the semiconductor device according to claim 7 ,
wherein the fourth potential is a ground potential.

10. The operation method of the semiconductor device according to claim 7 ,
wherein the fourth transistor comprises a metal oxide layer, a source electrode over and in electrical contact with the metal oxide layer and a drain electrode over and in electrical contact with the metal oxide layer.

11. An operation method for driving a semiconductor device,
wherein the semiconductor device comprises:
a first transistor comprising a backgate;
a second transistor comprising a backgate;
a third transistor;
a fourth transistor;
a first load;
a second load;
a first terminal;
a second terminal;
a third terminal;
a fourth terminal;
a fifth terminal;
a sixth terminal; and
a seventh terminal;

wherein the fourth transistor comprises a metal oxide layer, a source electrode over and in electrical contact with the metal oxide layer and a drain electrode over and in electrical contact with the metal oxide layer,
wherein a drain of the third transistor is electrically connected to a source of the first transistor and a source of the second transistor,
wherein a drain of the first transistor is electrically connected to the first load,
wherein a drain of the second transistor is electrically connected to the second load,
wherein the first terminal is electrically connected to a gate of the first transistor;
wherein the second terminal is electrically connected to a gate of the second transistor;
wherein the third terminal is electr

Assignees

• Semiconductor Energy Lab

Inventors

• Kato Kiyoshi
• Shionoiri Yutaka
• Atsumi Tomoaki
• Matsuzaki Takanori

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D1/00

  Resistors, capacitors or inductors · CPC title

• H10F39/026

  Wafer-level processing · CPC title