Surface mount resistors and methods of manufacturing same

Patent metadata

Field	Value
Publication number	US-10692632-B1
Application number	US-201916572052-A
Country	US
Kind code	B1
Filing date	Sep 16, 2019
Priority date	Oct 30, 2015
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Resistors and a method of manufacturing resistors are described herein. A resistor includes a resistive element and a plurality of conductive elements. The plurality of conductive elements are electrically insulated from one another via a dielectric material and thermally coupled to the resistive element via an adhesive material disposed between each of the plurality of conductive elements and a surface of the resistive element. The plurality of conductive elements is coupled to the resistive element.

First claim

What is claimed is:

1. A resistor comprising:
a resistive element having an upper surface, an opposite bottom surface, a first side, and an opposite second side; and
a first conductive layer adjacent the first side of the resistive element, the first conductive layer having a bottom surface at least a portion of which is thermally coupled to the upper surface of the resistive element by an adhesive, an outer portion of the first conductive layer swaged in an area adjacent the first side of the resistive element, a bottom surface of the outer portion of the first conductive layer extending toward the resistive element;
a second conductive layer adjacent the second side of the resistive element and separated by a gap from the first conductive layer, the second conductive layer having a bottom surface at least a portion of which is thermally coupled to the upper surface of the resistive element by an adhesive, an outer portion of the second conductive layer swaged in an area adjacent the second side of the resistive element, a bottom surface of the outer portion of the second conductive layer extending toward the resistive element;
a first electrode layer positioned along the bottom surface of the resistive element, adjacent the first side of the resistive element; and
a second electrode layer positioned along the bottom surface of the resistive element, adjacent the second side of the resistive element.

2. The resistor of claim 1 , further comprising:
a first solderable layer covering a first side of the resistor, the first solderable layer in contact with the first conductive layer, the resistive element, and the first electrode layer; and,
a second solderable layer covering a second side of the resistor, the second solderable layer in contact with the second conductive layer, the resistive element, and the second electrode layer.

3. The resistor of claim 2 , wherein the first solderable layer covers at least a portion of an upper surface of the first conductive layer, and at least a portion of a bottom surface of the first electrode layer.

4. The resistor of claim 3 , wherein the second solderable layer covers at least a portion of an upper surface of the second conductive layer, and at least a portion of a bottom surface of the second electrode layer.

5. The resistor of claim 1 , wherein each of the first conductive layer and the second conductive layer has upper and outer corners that are stepped, angled or rounded.

6. The resistor of claim 1 , wherein the outer portions of each of the first conductive layer and the second conductive layer have a first height above an upper surface of the adhesive, and wherein inner portions of each of the first conductive layer and the second conductive layer have a second height above an upper surface of the adhesive greater than the first height.

7. The resistor of claim 1 , wherein an outer portion of the bottom surface of the first conductive layer is positioned closer to the first electrode layer than an inner portion of the bottom surface of the first conductive layer, and wherein an outer portion of the bottom surface of the second conductive layer is positioned closer to the second electrode layer than an inner portion of the bottom surface of the second conductive layer.

8. A method of manufacturing a resistor, the method comprising:
providing a resistive element having an upper surface, a bottom surface, a first side, and an opposite second side; and
thermally coupling a first conductive layer to the upper surface of the resistive element adjacent the first side of the resistive element by an adhesive;
thermally coupling a second conductive layer to the upper surface of the resistive element adjacent the second side of the resistive element by an adhesive;
swaging an outer portion the first conductive layer so as to position an outer portion of a bottom surface of the first conductive layer in proximity to the resistive element in an area adjacent the first side of the resistive element;
swaging an outer portion the second conductive layer so as to position an outer portion of a bottom surface of the second conductive layer in proximity to the resistive element in an area adjacent the second side of the resistive element;
providing a first electrode layer along the bottom surface of the resistive element, adjacent the first side of the resistive element; and
providing a second electrode layer positioned along the bottom surface of the resistive element, adjacent the second side of the resistive element.

9. The method of claim 8 , further comprising the steps of:
plating a first solderable layer to a first side of the resistor, the first solderable layer in contact with the first conductive layer, the resistive element, and the first electrode layer; and,
plating a second solderable layer to a second side of the resistor, the second solderable layer in contact with the second conductive layer, the resistive element, and the second electrode layer.

10. The method of claim 9 , wherein the first solderable layer covers at least a portion of an upper surface of the first conductive layer, and at least a portion of a bottom surface of the first electrode layer.

11. The method of claim 10 , wherein the second solderable layer covers at least a portion of an upper surface of the second conductive layer, and at least a portion of a bottom surface of the second electrode layer.

12. The method of claim 8 , further comprising forming upper and outer corners of each of the first conductive layer and the second conductive layer as stepped, angled or rounded.

13. The method of claim 8 , further comprising forming each of the first conductive layer and the second conductive layer having the outer portions at a first height above an upper surface of the adhesive, and each of the first conductive layer and the second conductive layer having inner portions at a second height above an upper surface of the adhesive greater than the first height.

14. The method of claim 8 , further comprising positioning an outer portion of the bottom surface of the first conductive layer closer to the first electrode layer than an inner portion of the bottom surface of the first conductive layer, and positioning an outer portion of the bottom surface of the second conductive layer closer to the second electrode layer than an inner portion of the bottom surface of the second conductive layer.

Assignees

• Vishay Dale Electronics Llc

Inventors

• Smith Clark
• Wyatt Todd

Classifications

• H01C1/144

  the terminals or tapping points being welded or soldered · CPC title

• H01C1/142

  the terminals or tapping points being coated on the resistive element · CPC title

• H01C1/084 Primary

  using self-cooling, e.g. fins, heat sinks · CPC title

• H01C17/281

  by thick film techniques · CPC title

• H01C17/065

  by thick film techniques, e.g. serigraphy · CPC title