Semiconductor memory device, memory system, and refresh method thereof

Patent metadata

Field	Value
Publication number	US-10692561-B2
Application number	US-201816032361-A
Country	US
Kind code	B2
Filing date	Jul 11, 2018
Priority date	Nov 6, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a cell array including a plurality of DRAM cells to store data; and
refresh control logic configured to refresh the plurality of DRAM cells according to access scenario information provided from an external source,
wherein the refresh control logic is configured to determine a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells, and is configured to refresh the plurality of DRAM cells according to the determined refresh time, and
wherein the access scenario information includes:
a data retention time indicating a duration that the data should be retained in the plurality of DRAM cells; and
a total refresh time comprising the total duration of at least one non-operation period within the data retention time where external access to the plurality of DRAM cells is not permitted.

2. The semiconductor memory device of claim 1 , wherein the refresh control logic divides a portion of the total refresh time corresponding to a refresh window by a number of rows of the cell array to be refreshed to calculate the refresh time.

3. The semiconductor memory device of claim 1 , wherein, if the determined refresh time is shorter than predetermined value, the refresh control logic outputs refresh-unavailable information to an external device.

4. The semiconductor memory device of claim 1 , further comprising a refresh mode register in communication with the refresh control logic
including a refresh time register configured to store the total refresh time; and
a fail bit mode register configured to store a value indicative of an acceptable number of fail bits.

5. The semiconductor memory device of claim 4 , wherein the refresh control logic further includes:
a refresh clock controller configured to adjust a frequency of a refresh clock in response to at least one of the total refresh time and the acceptable number of fail bits indicated by the refresh mode register.

6. The semiconductor memory device of claim 1 , wherein the refresh control logic is configured to initiate refresh operations of the plurality of DRAM cells in response to an externally received refresh enable signal.

7. The semiconductor memory device of claim 1 , further comprising:
a temperature sensor configured to sense an operating temperature of the semiconductor memory device and to provide the sensed operating temperature to the refresh control logic,
wherein the refresh control logic is configured to adjust the refresh time according to the sensed operating temperature.

8. The semiconductor memory device of claim 1 , further comprising:
a command decoder configured to decode a command received from the external source and to generate an internal control signal in response to the decoded command,
wherein the command decoder is not configured to decode a refresh command to initiate a refresh operation.

9. The semiconductor memory device of claim 8 , further comprising a refresh mode register configured to store the access scenario information.

10. A memory system comprising:
a host configured to record and read data in a buffer during a data retention time depending on an access scenario; and
a DRAM in communication with the host to receive, store and send the data,
wherein the DRAM is provided as the buffer of the host and is configured to receive time information of the access scenario, wherein the DRAM is configured to perform self-refresh operations during at least one non-operation period of the access scenario on a memory area where the data received from the host is stored,
wherein the host is configured to enable the self-refresh operation of the DRAM by providing a refresh enable signal to the DRAM,
wherein the time information of the access scenario includes duration information of the at least one non-operation period of the access scenario, and
wherein the DRAM includes refresh control logic configured to calculate a refresh time corresponding to a time duration between initiating refresh of sequentially refreshed rows of the memory area using the duration information of the at least one non-operation period of the access scenario.

11. The memory system of claim 10 , wherein the host is an image processing device that uses the DRAM as a frame buffer to store frames of image data.

12. The memory system of claim 10 , wherein the refresh control logic is configured to calculate the refresh time also using at least one of an operating temperature of the DRAM and a number of allowable fail bits of the DRAM.

13. The memory system of claim 10 , wherein the DRAM includes:
a first memory area that is configured to be accessed at a timing depending on the access scenario; and
a second memory area that is configured to be accessed at a timing dependent on receiving external commands outside of the access scenario.

14. The memory system of claim 13 , wherein the host is configured to provide access area information to the DRAM and the DRAM is configured to calculate the refresh time for a self-refresh mode for the first memory area, wherein the calculated refresh time is not used in refreshing the second memory.

15. The memory system of claim 14 , wherein the DRAM is configured to perform refresh operations of the second memory area as auto refresh operations in response to receiving corresponding auto refresh commands provided by the host.

16. A refresh method of a semiconductor memory device in which data are written and read based on a scenario, the method comprising:
receiving a data retention time according to an access scenario and a length of a non-operation period included in the data retention time from an external source;
calculating a refresh time of a memory area where the data are written using the length of the non-operation period and a characteristic parameter of memory cells; and
refreshing the memory area at a timing depending on the calculated refresh time during the non-operation period.

17. The method of claim 16 , wherein, in the calculating of the refresh time, the refresh time is determined with reference to a number of acceptable error bits within the data.

18. The method of claim 16 , wherein, in the calculating of the refresh time, the refresh time is determined based upon an operation temperature of the semiconductor memory device.

19. The method of claim 16 , wherein, in the refreshing, the semiconductor memory device refreshes the memory area by initiating refresh operations when a refresh enable signal is activated during a non-operation period, wherein the timing of the initiation of the refresh operations does not correspond to receipt of any externally received refresh commands.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Min-Soo
• Seo Eunsung
• Bae Seungjun

Classifications

• H04N25/773

  comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title