OLED display panel and OLED display device

Patent metadata

Field	Value
Publication number	US-10692439-B2
Application number	US-201816153646-A
Country	US
Kind code	B2
Filing date	Oct 5, 2018
Priority date	Oct 26, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

The present disclosure relates to an OLED display panel and an OLED display device in which a GIP driving circuit is arranged in an active area in order to minimize a bezel size and a GIP signal is applied to the GIP driving circuit arranged in the active area using a single-sided COF, and the OLED display panel includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; stages of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions corresponding to the scan lines in the active area to supply scan pulses to the scan lines; and a non-active area including a pad part, a link part and a LOG part, wherein the pad part includes a gate pad part for supplying various control signals to the stages of the GIP driving circuit, and a data pad part for supplying a data voltage to each data line, and wherein the non-active area includes a plurality of signal lines extended from the gate pad part via the link part to the LOG part in order to supply various control signals to the GIP parts is arranged.

First claim

What is claimed is:

1. An OLED display panel comprising:
an active area where a plurality of data lines, a plurality of scan lines intersecting the plurality of data lines, and a plurality of sub-pixels are arranged at each intersection;
a plurality of stages of a gate in panel (GIP) driving circuit distributed and arranged in a plurality of unit pixel regions corresponding to the plurality of scan lines in the active area to supply a plurality of scan pulses to the plurality of scan lines;
a non-active area where a pad part including a gate pad part and a data pad part, a link part and a line on glass (LOG) part are arranged wherein the non-active area includes a plurality of signal lines extended from the gate pad part to the LOG part via the link part to supply a plurality of control signals to the plurality of stages, and
a reference voltage supply line supplying a reference voltage to each sub-pixel, and a plurality of first and second constant voltage supply lines supplying first and second constant voltages to each sub-pixel,
wherein the gate pad part supplies the plurality of control signals to the plurality of stages of the GIP driving circuit and the data pad part supplies a data voltage to each data line, and
wherein the data pad part includes a plurality of pads connected to the reference voltage supply line and a plurality of pads connected to the plurality of first and second constant voltage supply lines.

2. The OLED display panel according to claim 1 , wherein each of the plurality of unit pixel regions includes at least three sub-pixels, a GIP part in which an element constituting each stage of the GIP driving circuit is arranged, and a GIP internal interconnection line part in which connection lines for connecting elements of the stage are arranged.

3. The OLED display panel according to claim 1 , wherein the plurality of signal lines is extended from the gate pad part and bypasses the pad part to extend to the LOG part via the link part.

4. The OLED display panel according to claim 1 , wherein the link part includes a link line penetrating the pad part to connect one of the plurality of signal lines to the GIP parts.

5. The OLED display panel according to claim 1 , wherein each stage of the GIP driving circuit comprises:
an output buffer including a pull-up transistor, a pull-down transistor and a bootstrapping capacitor,
wherein the bootstrapping capacitor bootstraps a first node of one of the stages of the GIP driving circuit such that the first node has a high potential when a clock signal for a scan pulse output is applied at a high level.

6. The OLED display panel according to claim 5 , wherein the bootstrap capacitor is connected between a gate electrode and a source electrode of the pull-up transistor.

7. An OLED display device comprising:
an active area where a plurality of data lines, a plurality of scan lines intersecting the plurality of data lines, and a plurality of sub-pixels are arranged at each intersection;
a plurality of stages of a gate in panel (GIP) driving circuit distributed and arranged in a plurality of unit pixel regions corresponding to the plurality of scan lines in the active area to supply a plurality of scan pulses to the plurality of scan lines; and
a non-active area where a pad part including a gate pad part and a data pad part, a link part and a line on glass (LOG) part are arranged wherein the non-active area includes a plurality of signal lines extended from the gate pad part to the LOG part via the link part to supply a plurality of control signals to the plurality of stages, wherein the gate pad part supplies the plurality of control signals to the plurality of stages of the GIP driving circuit and the data pad part supplies a data voltage to each data line; and
a plurality of chip on films (COFs) having source drive ICs mounted thereon and connected to the pad part,
wherein the plurality of signal lines in the non-active area is formed at left and right sides of the COFs, and a plurality of first and second constant voltage supply lines is arranged at a center of the COFs.

8. An OLED display panel comprising:
a plurality of stages of a gate in panel (GIP) driving circuit arranged in a plurality of unit pixel regions corresponding to a plurality of scan lines in the active area and supplies a plurality of scan pulses to the plurality of scan lines;
a plurality of data lines intersecting the plurality of scan lines, and a plurality of sub-pixels are arranged at each intersection in an active area; and
a pad part disposed at a non-active area and including a gate pad part supplying the plurality of control signals to the plurality of stages of the GIP driving circuit and a data pad part supplying a data voltage to each data line;
a link part disposed at the non-active area and extended between a plurality of data lines in the active area;
a line on glass (LOG) part disposed at the non-active area and transmitting a clock signal, a gate start signal, a gate high voltage and a gate low voltage supplied from a timing controller to the GIP driving circuit; and
a plurality of signal lines arranged at the non-active area and extended from the gate pad part to the LOG part through the link part and supplies a plurality of control signals to the plurality of stages.

9. The OLED display panel according to claim 8 , further comprising a plurality of unit pixel regions each including at least three sub-pixels, a GIP part in which an element constituting each stage of the GIP driving circuit is arranged, and a GIP internal interconnection line part in which connection lines for connecting elements of the stage are arranged.

10. The OLED display panel according to claim 8 , further comprising a reference voltage supply line supplying a reference voltage to each sub-pixel, and a plurality of first and second constant voltage supply lines supplying first and second constant voltages to each sub-pixel at the active area.

11. The OLED display panel according to claim 10 , wherein the data pad part includes a plurality of pads connected to the reference voltage supply line and a plurality of pads connected to the plurality of first and second constant voltage supply lines.

12. The OLED display panel according to claim 8 , wherein the plurality of signal lines is extended from the gate pad part and bypasses the pad part to extend to the LOG part via the link part.

13. The OLED display panel according to claim 8 , wherein the link part includes a link line penetrating the pad part to connect one of the plurality of signal lines to the GIP parts.

14. The OLED display panel according to claim 8 , wherein each stage of the GIP driving circuit comprises:
an output buffer including a pull-up transistor, a pull-down transistor and a bootstrapping capacitor,
wherein the bootstrapping capacitor bootstraps a first node of one of the stages of the GIP driving circuit such that the first node has a high potential when a clock signal for a scan pulse output is applied at a high level.

15. The OLED display panel according to claim 14 , wherein the bootstrap capacitor is connected between a gate electrode and a source electrode of the pull-up transistor.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Kyung-Min
• Han In-Hyo

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title