Display panel

Patent metadata

Field	Value
Publication number	US-2016307488-A1
Application number	US-201615099487-A
Country	US
Kind code	A1
Filing date	Apr 14, 2016
Priority date	Apr 17, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

There is provided a display panel including a plurality of white subpixels configured to display a white image, a gate line connected with the white subpixels and extended in a row direction, and an in-pixel gate driver including in-pixel elements exclusively in the white subpixels and connected with the gate line to supply a gate signal to the gate line.

First claim

What is claimed is:

1 . A display panel comprising:
a plurality of white subpixels configured to display a white image; a gate line connected with the white subpixels and extended in a row direction; and an in-pixel gate driver comprising in-pixel elements exclusively in the white subpixels and connected with the gate line to supply a gate signal to the gate line.

2 . The display panel according to claim 1 ,
wherein the in-pixel elements are in a device embedded area of each of the white subpixels, and wherein each of the white subpixels comprises a white pixel electrode in an electrode area of each of the white subpixels, the electrode area not overlapping with the device embedded area.

3 . The display panel according to claim 2 ,
wherein each of the white subpixels comprises a device driving circuit in a circuit area of each of the white subpixels, and wherein the electrode area does not overlap with the device embedded area.

4 . The display panel according to claim 1 ,
wherein the gate line comprises first to n'th gate lines, and wherein the in-pixel gate driver comprises first to n'th in-pixel gate driver units that supply corresponding gate signals of the gate signal to the first to n'th gate lines, where n is a natural number larger than or equal to 2.

5 . The display panel according to claim 4 , wherein each of the first to n'th in-pixel gate driver units is comprises p members, where p is a natural number larger than or equal to 2.

6 . The display panel according to claim 1 , wherein the in-pixel gate driver is comprises a plurality of in-pixel gate driver units provided along the row direction.

7 . The display panel according to claim 6 , wherein each of the plurality of in-pixel gate driver units comprise members corresponding to k subpixels in the row direction, where k is a natural number.

8 . The display panel according to claim 7 , wherein k is determined from characteristics of the gate line.

9 . The display panel according to claim 1 ,
wherein the gate line comprises a first gate line and a second gate line adjacent to the first gate line in a column direction, and wherein the in-pixel gate driver is between the first and second gate lines, and is configured to use a first gate signal of the gate signal to generate a second gate signal of the gate signal, the first and second signals being received from the first and second gate lines, respectively.

10 . The display panel according to claim 9 , wherein the in-pixel elements comprise a first transistor connected with the first gate line and configured to supply the first gate signal.

11 . The display panel according to claim 10 , further comprising an off-voltage line configured to supply an off-voltage,
wherein the in-pixel element comprises a second transistor connected with the off-voltage line and configured to supply the off-voltage from the off-voltage line to the second gate line.

12 . The display panel according to claim 11 , further comprising: a positive clock line configures to supply a positive clock signal; and a negative clock line configured to supply a negative clock signal having a phase reverse that of the positive clock,
wherein the in-pixel element comprises a third transistor that comprises a source electrode connected with the positive clock line and a drain electrode connected with the second gate line, and wherein the second transistor comprises a gate electrode connected with the negative clock line, a source electrode connected with the off-voltage line, and a drain electrode connected with the second gate fine.

13 . The display panel according to claim 12 ,
wherein the off-voltage line is parallel with the row direction, and wherein the positive and negative clock fines are parallel with the column direction.

14 . The display panel according to claim 1 , further comprising a plurality of pixel groups,
wherein each of the pixel groups comprise the white subpixel and a plurality of pixels, each of the pixels having a plurality of color subpixels to display a color image.

15 . The display panel according to claim 14 , wherein a left pixel and a right pixel of the plurality of pixels are at opposite sides of the white subpixel.

16 . The display panel according to claim 15 , wherein the left pixel and the right pixel of each of the pixel groups are configured to share the white subpixel of each of the pixel groups.

17 . The display panel according to claim 15 , wherein each of the left and right pixels comprises a red subpixel, a green subpixel, and a blue subpixel respectively displaying a red image, a green image, and a blue image.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Se-Hyang
• Kwak Heejune
• Jung Kwang-Chul
• Lim Sang-Uk
• Jeong Junki

Classifications

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title