Wirelessly synchronized clock networks

Patent metadata

Field	Value
Publication number	US-10687293-B2
Application number	US-201916363116-A
Country	US
Kind code	B2
Filing date	Mar 25, 2019
Priority date	Mar 31, 2017
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit. The respective second clock generating circuit may be configured to generate a respective intermediate clock signal, synchronize the respective intermediate clock signal with the recovered synchronization signal, and generate a respective second clock signal that provides internal clocking for the second device.

First claim

The invention claimed is:

1. A system comprising:
a first device comprising a first clock generating circuit and a transmitter circuit, wherein (i) said first clock generating circuit is configured to generate a first clock signal, (ii) said first clock signal provides internal clocking for said first device, and (iii) said transmitter circuit is configured to generate a synchronization signal in response to said first clock signal and wirelessly transmit a broadcast signal communicating only said synchronization signal; and
a plurality of second devices, each second device comprising a respective receiver circuit and a respective second clock generating circuit, wherein (i) said respective receiver circuit is configured to receive said broadcast signal and present a recovered synchronization signal to a first input of a comparison circuit of said respective second clock generating circuit, (ii) said respective second clock generating circuit is configured to generate a respective intermediate clock signal, present the respective intermediate clock signal to a second input of the comparison circuit, synchronize said respective intermediate clock signal with said recovered synchronization signal based on an output signal of said comparison circuit, and generate a respective second clock signal that provides internal clocking for said second device in response to said respective intermediate clock signal, and (iii) said comparison circuit is configured to compare the recovered synchronization signal received at the first input with the respective intermediate clock signal received at the second input by performing a frequency comparison, a phase comparison, or a phase and frequency comparison.

2. The system according to claim 1 , wherein said synchronization signal comprises a frequency lower than said first clock signal and said respective second clock signals of said second devices are synchronized to said first clock signal of said first device in response to said recovered synchronization signal.

3. The system according to claim 1 , wherein said synchronization signal has a frequency measured in kHz.

4. The system according to claim 1 , wherein said synchronization signal has a frequency measured in MHZ.

5. The system according to claim 1 , wherein said synchronization signal has a frequency measured in GHz.

6. The system according to claim 1 , wherein said synchronization signal is modulated on a carrier signal by said transmitter circuit.

7. The system according to claim 1 , wherein said first device comprises a motherboard and said second devices comprise PCIe cards.

8. The system according to claim 1 , wherein said first device and said second devices are components of a multi-chip module.

9. The system according to claim 1 , wherein said first device and said second devices are components distributed around a vehicle.

10. The system according to claim 1 , wherein said first device and said second devices comprise separate systems located within a broadcast range of said transmitter circuit.

11. A method of wirelessly synchronizing a clock network comprising:
generating a first clock signal using a first clock generator of a first device;
generating a synchronization signal in response to said first clock signal and wirelessly broadcasting a broadcast signal communicating only said synchronization signal;
receiving said broadcast signal and generating a recovered synchronization signal at each of a plurality of second devices;
generating respective intermediate clock signals using respective second clock generators of each of said second devices;
presenting said recovered synchronization signal and said respective intermediate clock signals to a first input and a second input, respectively, of a comparison circuit of said respective second clock generators, wherein said comparison circuit generates an output signal by performing a frequency comparison, a phase comparison, or a phase and frequency comparison between the recovered synchronization signal received at the first input and the respective intermediate clock signal received at the second input;
synchronizing said respective intermediate clock signals with said recovered synchronization signal based on said output signal from said comparison circuit in said respective second clock generators; and
generating respective second clock signals that provide internal clocking for said second devices in response to said respective intermediate clock signals.

12. The method according to claim 11 , wherein said synchronization signal comprises a frequency lower than said first clock signal and said respective second clock signals of said second devices are synchronized to said first clock signal of said first device in response to said recovered synchronization signal.

13. The method according to claim 11 , wherein said synchronization signal has a frequency measured in kHz.

14. The method according to claim 11 , wherein said synchronization signal has a frequency measured in MHZ.

15. The method according to claim 11 , wherein said synchronization signal has a frequency measured in GHz.

16. The method according to claim 11 , wherein said synchronization signal is modulated on a carrier signal by a transmitter circuit.

17. The method according to claim 11 , wherein said synchronization signal is broadcast as an infrared signal.

18. The method according to claim 11 , wherein said synchronization signal comprises a predetermined bit sequence.

19. The method according to claim 11 , wherein said synchronization signal is broadcast as an ultrasonic signal.

20. The method according to claim 11 , wherein a timing generated by said second clock signals associated with said one or more second devices is matched to said first clock signal in response to said synchronization signal.

Assignees

• Integrated Device Tech

Inventors

• Bal Jagdeep
• Ayache Elie
• Van Keulen Eduard

Classifications

• H04L7/04

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04W56/0015 Primary

  one node acting as a reference for the others · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title