Secure processor and a program for a secure processor

Patent metadata

Field	Value
Publication number	US-10685145-B2
Application number	US-201916382739-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Jun 30, 2004
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

First claim

The invention claimed is:

1. A processor configured to operate in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited, the processor comprising:
an execution unit configured to output a first virtual address; and
a memory access control unit configured to access a first physical address corresponding to the first virtual address by referring to a flag of a page table entry in a translation look-aside buffer,
wherein, only in the first mode, the memory access control unit permits an access to the first physical address within the secure address space in which the flag of the page table entry is set to a value indicating that a corresponding address space is secure, and
wherein, by executing a first instruction code stored in the secure address space in the first mode, a second instruction code is checked in the first mode before the second instruction code is executed in the second mode.

2. The processor according to claim 1 ,
wherein the first instruction code is stored in a non-rewritable memory.

3. The processor according to claim 1 ,
wherein a mode switching between the first mode and the second mode is triggered by an interruption.

4. The processor according to claim 3 , comprising
a mode register configured to indicate whether the processor is in the first mode or in the second mode,
wherein the mode register is set in response to the interruption.

5. The processor according to claim 1 ,
wherein the page table entry further includes a virtual address, a physical address corresponding to the virtual address, and an identifier that indicates secure context.

6. The processor according to claim 1 ,
wherein the second instruction code is executed in the second mode after the second instruction code is checked.

7. The processor according to claim 1 ,
wherein the first mode is a secure mode and the second mode is a normal mode.

8. The processor according to claim 1 ,
wherein the memory access control unit further includes a cache memory containing at least a tag and data corresponding to the tag, and the data is directly returned to the execution unit without accessing outside of the memory access control unit when cache is hit.

Assignees

• Socionext Inc

Inventors

• Goto Seiji
• Kamada Jun
• Tamiya Taiji

Classifications

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1408

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title