Removable test and diagnostics circuit

Patent metadata

Field	Value
Publication number	US-10684664-B2
Application number	US-201415314785-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Jul 31, 2014
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.

First claim

What is claimed:

1. A backup power testing and diagnostic system, comprising:
a plurality of nodes, wherein a node within the plurality of nodes contains at least one non-volatile dual inline memory module (NV-DIMM) slot;
a battery module;
a backup power control module having instructions stored in a non-transitory storage medium and executed by a processing resource to determine, based on monitored power, a backup power demand of at least one load to the node and to provide backup power from the battery module to the node; and
a test and diagnostics circuit removably located in the NV-DIMM slot to test the battery module and the node.

2. The backup power testing and diagnostic system of claim 1 , wherein the test and diagnostics circuit includes logic to perform a communication protocol conversion between the node and the test and diagnostics circuit, including a direct current (DC) level conversion.

3. The backup power testing and diagnostic system of claim 1 , wherein the test and diagnostics circuit includes logic to monitor system power of a host and a backup power status of the battery module.

4. The backup power testing and diagnostic system of claim 1 , wherein the test and diagnostics circuit is a test and diagnostics circuit card having double data rate 4 (DDR4) form factor which is removably located in a 288 pin NV-DIMM slot and having a pin to receive control signals from a non-dedicated pin to the 288 pin NV-DIMM slot.

5. The backup power testing and diagnostic system of claim 4 , wherein the test and diagnostics circuit includes logic to:
receive and hold a test enable signal from the non-dedicated pin;
and
store monitored test information at selected intervals on the test and diagnostics circuit.

6. The backup power testing and diagnostic system of claim 1 ,
wherein the test and diagnostics circuit includes logic to select a load from among multiple load values to test the battery module.

7. The backup power testing and diagnostic system of claim 1 ,
wherein the test and diagnostics circuit includes logic to receive a test enable signal from a non-dedicated pin of the NV-DIMM slot.

8. The backup power testing and diagnostic system of claim 1 ,
wherein the test and diagnostics circuit includes logic to store monitored test information at selected intervals on the test and diagnostics circuit.

9. The backup power testing and diagnostic system of claim 1 , comprising:
a primary power supply to supply power to the plurality of nodes,
wherein the battery module is to supply backup power to the plurality of nodes.

10. A test and diagnostic circuit, comprising:
a controller;
a power monitor coupled to the controller;
a load switch to selectably implement a load from among multiple load values to test a server node; and
circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the server node.

11. The test and diagnostics circuit of claim 10 , wherein the controller includes logic to:
hold the test enable signal received to the non-dedicated pin;
perform a backup power supply test in a stand-alone test mode;
perform a backup power supply test in a plug-in test mode; and
perform a real-time host power supply test.

12. The test and diagnostics circuit of claim 10 , wherein the circuitry further includes second circuitry to:
perform communication protocol conversion from the server node to the controller;
store monitored test information at selected intervals on the test and diagnostics circuit;
visually indicate information relative to the test operation;
switch power externally provided to the test and diagnostics circuit; and
upload firmware to the controller.

13. The test and diagnostics circuit of claim 12 , wherein the controller includes logic to perform system diagnostics on a host power supply and a backup power supply.

14. The test and diagnostic circuit of claim 10 ,
wherein the test and diagnostic circuit has a double data rate 4 (DDR4) form factor and is removably insertable in the NV-DIMM slot, which is a 288 pin NV-DIMM slot.

15. A method of testing backup power and diagnostics for a plurality of nodes, comprising:
receiving at a test and diagnostics circuit, removably located in a non-volatile dual inline memory module (NV-DIMM) slot of at least one of the plurality nodes, a test enable signal from a backup power control module associated with a backup power supply;
registering, by the test and diagnostics circuit, an available level of the backup power supply;
selecting, by the test and diagnostics circuit, a particular load to emulate from among multiple load scenarios;
activating, by the test and diagnostics circuit, a test duration timer; and
monitoring, by the test and diagnostics circuit, a power demand for the at least one node under the selected particular load and in reference to the level of the backup power supply.

16. The method of claim 15 , wherein receiving the test enable signal includes receiving the test enable signal to a non-dedicated pin in a NV-DIMM slot according to a double data rate 4 (DDR4) form factor.

17. The method of claim 16 , wherein the method includes:
verifying a test mode selected from a plug-in test mode, a stand-alone test mode, and a run-time test mode; and
locking a test enable signal on in the plug-in test mode.

18. The method of claim 15 , wherein selecting the particular load includes
providing a test and diagnostics circuit for each of the plurality of nodes and selecting a load for each of the plurality of nodes independently, wherein selecting the load for each of the plurality of nodes independently includes selecting different load levels for at least two of the plurality of nodes.

19. The method of claim 15 , wherein the method further includes verifying a communication capability between the at least one node and a controller of the backup power supply using an interface and a chassis controller associated with the plurality of nodes.

20. The method of claim 15 , wherein monitoring the power demand includes:
monitoring a power consumption from the backup power supply by the at least one node; and
storing information on the power consumption in a non-volatile memory at a selected interval on the test and diagnostics circuit.

Assignees

• Hewlett Packard Entpr Dev Lp
• Hewlett Packard Entpr Develepment Lp

Inventors

• Venugopal Raghavan V
• Raymond Patrick A
• Hallowell William C
• Wang Han
• Chiang Chin-Lung
• Wang Jyun-Jie

Classifications

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title