Power amplifier system

Patent metadata

Field	Value
Publication number	US-10680565-B2
Application number	US-201816022816-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

First claim

What is claimed is:

1. A power amplifier system comprising:
a power amplifier having a first signal input and a first signal output;
main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input; and
peak bias circuitry configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range, and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

2. The power amplifier system of claim 1 wherein the first input power range has lower power levels than the second input power range.

3. The power amplifier system of claim 1 wherein the first input power range and the second input power range comprise a total input power range, and the first input power range spans a greater portion of the total input power range than does the second input power range.

4. The power amplifier system of claim 1 wherein the power amplifier is configured to operate as a differential power amplifier that includes a second signal input and a second signal output.

5. The power amplifier system of claim 4 wherein the main bias circuitry is further configured to provide a first portion of a second bias signal through a third bias output coupled to the second signal input, and the peak bias circuitry is further configured to provide a second portion of the second bias signal through a fourth bias output coupled to the second signal input such that the first portion of the second bias signal is greater than the second portion of the second bias signal over the first input power range, and the second portion of the second bias signal is greater than the first portion of the second bias signal over the second input power range that is greater than the first input power range.

6. The power amplifier system of claim 5 wherein the main bias circuitry comprises:
a first bias reference circuit configured to provide a first reference voltage to a first bias reference node; and
a first bias generator comprising:
a first transistor having a first control terminal coupled to the first bias reference node, a first current terminal coupled to a power supply rail, and a second current terminal coupled to the first bias output; and
a second transistor having a second control terminal coupled to the first bias reference node, a third current terminal coupled to the power supply rail, and a fourth current terminal coupled to the second bias output.

7. The power amplifier system of claim 6 further including a first filter capacitor coupled between the first bias reference node and a fixed voltage node.

8. The power amplifier system of claim 6 wherein the first bias reference circuit is a pair of stacked transistors that are each in a diode configuration coupled between the first bias reference node and a fixed voltage node.

9. The power amplifier system of claim 8 wherein the pair of stacked transistors are bipolar junction transistors.

10. The power amplifier system of claim 6 wherein the first transistor of the first bias generator and the second transistor of the first bias generator are bipolar junction transistors.

11. The power amplifier system of claim 6 wherein the peak bias circuitry comprises:
a second bias reference circuit configured to provide a second reference voltage to a second bias reference node; and
a second bias generator comprising:
a third transistor having a third control terminal coupled to the second bias reference node, a fifth current terminal coupled to the power supply rail, and a sixth current terminal coupled to the third bias output; and
a fourth transistor having a fourth control terminal coupled to the second bias reference node, a seventh current terminal coupled to the power supply rail, and a fourth current terminal coupled to the fourth bias output.

12. The power amplifier system of claim 11 further including an offset bias generator coupled between the third control terminal and the second bias reference node, wherein the offset bias generator is configured to generate a bias offset that sets a first point at which the first portion of the first bias signal and the second portion of the first bias signal are equal.

13. The power amplifier system of claim 12 wherein the offset bias generator is coupled between the fourth control terminal and the second bias reference node, wherein the bias offset generated by the offset bias generator sets a second point at which the first portion of the second bias signal and the second portion of the second bias signal are equal.

14. The power amplifier system of claim 11 further including a second filter capacitor coupled between the second bias reference node and a fixed voltage node.

15. The power amplifier system of claim 11 wherein the second bias reference circuit is a pair of stacked transistors that are each in a diode configuration.

16. The power amplifier system of claim 15 wherein the pair of stacked transistors are bipolar junction transistors.

17. The power amplifier system of claim 11 wherein the third transistor of the second bias generator and the fourth transistor of the second bias generator are bipolar junction transistors.

18. The power amplifier system of claim 6 wherein the first bias reference circuit comprises:
a first bipolar junction transistor having a first base coupled to the first bias reference node, a first collector, and a first emitter;
a second bipolar junction transistor having a second base coupled to the first emitter, and a second collector coupled to the second base, and a second emitter coupled to a fixed voltage node; and
a resistor coupled between the first bias reference node and the first collector.

19. The power amplifier system of claim 18 wherein the peak bias circuitry includes a second bias generator comprising:
a third transistor having a third control terminal coupled to the first collector, a fifth current terminal coupled to the power supply rail, and a sixth current terminal coupled to the third bias output; and
a fourth transistor having a fourth control terminal coupled to the first collector, a seventh current terminal coupled to the power supply rail, and a eighth current terminal coupled to the fourth bias output wherein a bias reference voltage at the first collector sets a bias offset for the second bias generator.

20. The power amplifier system of claim 18 wherein the resistor has a variable resistance for adjusting the bias reference voltage.

Assignees

• Qorvo Us Inc

Inventors

• Scott Baker
• Oshima Hideya
• Maxim George
• Leipold Dirk Robert Walter

Classifications

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title