Power amplifier with improved low bias mode linearity

Patent metadata

Field	Value
Publication number	US-9337787-B2
Application number	US-201414304149-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jun 19, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.

First claim

What is claimed is:

1. Circuitry comprising:
a power amplifier including an input node and an output node;
an input capacitor coupled to the input node of the power amplifier, such that the power amplifier is configured to receive an RF input signal via the input capacitor;
a selectable impedance network comprising:
a first selectable impedance node;
a second selectable impedance node coupled to the input node of the power amplifier;
an impedance element coupled between the first selectable impedance node and the second selectable impedance node;
a switching element coupled in parallel with the impedance element between the first selectable impedance node and the second selectable impedance node; and

biasing circuitry coupled to the first selectable impedance node of the selectable impedance network, wherein:
the circuitry is configured to operate in a low power operating mode in which the biasing circuitry supplies a first biasing current to the input node of the power amplifier through the impedance element in the selectable impedance network; and
the circuitry is configured to operate in a high power operating mode in which the biasing circuitry supplies a second biasing current to the input node of the power amplifier at least partially through the switching element in the selectable impedance network.

2. The circuitry of claim 1 wherein the power amplifier is configured to amplify the RF input signal and deliver the amplified RF input signal to the output node.

3. The circuitry of claim 1 wherein the first biasing current is less than the second biasing current.

4. The circuitry of claim 1 wherein the impedance provided by the selectable impedance network in the low power operating mode is higher than the impedance provided by the selectable impedance network in the high power operating mode.

5. The circuitry of claim 4 wherein the impedance provided by the selectable impedance network in the high power operating mode is less than half of the impedance provided by the selectable impedance network in the low power operating mode.

6. The circuitry of claim 1 wherein a power range of the RF input signal is between −50 dBm and +15 dBm.

7. The circuitry of claim 6 wherein the power range of the RF input signal is between −20 dBm and +8 dBm.

8. The circuitry of claim 1 wherein the impedance provided by the selectable impedance network in the low power operating mode and the impedance provided by the selectable impedance network in the high power operating mode are primarily resistive impedances.

9. The circuitry of claim 1 wherein:
the power amplifier is an RF transistor including a base contact, an emitter contact, and a collector contact;
the input node of the power amplifier is the base contact;
the output node of the power amplifier is the collector contact; and
the emitter contact of the power amplifier is coupled to ground.

10. The circuitry of claim 1 wherein the switching element is a transistor.

11. The circuitry of claim 1 wherein the biasing circuitry comprises:
a biasing current source;
a first diode including a cathode contact coupled to ground and an anode contact;
a second diode including a cathode contact coupled to the anode contact of the first diode and an anode contact coupled to the biasing current source; and
a biasing transistor including a base contact coupled to the anode of the second diode, an emitter contact coupled to the first selectable impedance node of the selectable impedance network, and a collector contact coupled to a power supply.

12. The circuitry of claim 11 wherein the first diode and the second diode are diode connected transistors.

13. The circuitry of claim 1 wherein the value of the impedance provided by the selectable impedance network in the low power operating mode is selected such that the effective capacitance of the input capacitor as the RF input signal level increases is reduced over a defined input power range in the low power operating mode.

14. The circuitry of claim 1 wherein the value of the impedance provided by the selectable impedance network in the high power operating mode is selected such that the effective capacitance of the input capacitor is substantially constant over the defined input power range in the high power operating mode.

15. Circuitry comprising:
a power amplifier including an input node and an output node;
an input capacitor coupled to the input node of the power amplifier, such that the power amplifier is configured to receive an RF input signal via the input capacitor;
a selectable impedance network comprising:
a first selectable impedance node;
a second selectable impedance node;
a third selectable impedance node coupled to the input node of the power amplifier;
a first impedance element coupled between the first selectable impedance node and the third selectable impedance node;
a second impedance element coupled between the second selectable impedance node and the third selectable impedance node;

low power operating mode biasing circuitry coupled to the first selectable impedance node; and
high power operating mode biasing circuitry coupled to the second selectable impedance node, wherein:
the circuitry is configured to operate in a low power operating mode in which the low power operating mode biasing circuitry is active to deliver a first biasing current to the input node of the power amplifier through the first impedance element in the selectable impedance network; and
the circuitry is configured to operate in a high power operating mode in which the high power operating mode biasing circuitry is active to deliver a second biasing current to the input node of the power amplifier through the second impedance element in the selectable impedance network.

16. The circuitry of claim 15 wherein the power amplifier is configured to amplify the RF input signal and deliver the amplified RF input signal to the output node.

17. The circuitry of claim 15 wherein the first biasing current is less than the second biasing current.

18. The circuitry of claim 15 wherein the first impedance element is larger than the second impedance element.

19. The circuitry of claim 18 wherein the second impedance element is less than half of the first impedance element.

20. The circuitry of claim 15 wherein a power range of the RF input signal is between −50 dBm and +15 dBm.

21. The circuitry of claim 20 wherein the power range of the RF input signal is between −20 dBm and +8 dBm.

22. The circuitry of claim 15 wherein the first impedance element and the second impedance element are resistors.

23. The circuitry of claim 15 wherein:
the power amplifier is an RF transistor including a base contact, an emitter contact, and a collector contact;
the input node of the power amplifier is the base contact;
the output node of the power amplifier is the collector contact; and
the emitter contact of the power amplifier is coupled to ground.

24. The circuitry of claim 15 wherein the low power operating mode biasing circuitry comprises:
a low power operating mode biasing current source;
a first diode including a cathode contact coupled to ground and an anode contact;
a second diode including a cathode contact coupled to the anode contact of the first diode and an anode contact;
a biasing transistor including a base contact coupled to the anode of the second diode, an emitter contact coupled to the first selectable impe

Assignees

• Rf Micro Devices Inc

Inventors

• Schooley Derek
• Hietala Alexander Wayne

Classifications

• H03F3/21 Primary

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03G3/30

  in amplifiers having semiconductor devices · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title

• H03F3/191

  Tuned amplifiers (H03F3/193, H03F3/195 take precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title