Multilayer hardmask for high performance MRAM devices

Patent metadata

Field	Value
Publication number	US-10680169-B2
Application number	US-201816007644-A
Country	US
Kind code	B2
Filing date	Jun 13, 2018
Priority date	Jun 13, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first electrically conductive structure embedded in a first interconnect dielectric material layer and located in a magnetoresistive random access memory (MRAM) device area;
a conductive landing pad located on a surface of the first electrically conductive structure in the MRAM device area;
a magnetic tunnel junction (MTJ) structure located on the conductive landing pad;
a MTJ cap located on the MTJ structure;
a multilayered hardmask structure located on the MTJ cap, the multilayered hardmask structure comprising a patterned halogen barrier hardmask layer and a patterned upper hardmask layer, and wherein the multilayered hardmask structure has outermost sidewalls that are vertically aligned to outermost sidewalls of both of the MTJ cap and the MTJ structure; and
a second interconnect dielectric material layer located above the first interconnect dielectric material layer and surrounding the MTJ structure, the MTJ cap and the multilayered hardmask structure, wherein a second electrically conductive structure is embedded in the second interconnect dielectric material layer and is in contact with an upper portion of the patterned upper hardmask layer.

2. The semiconductor structure of claim 1 , wherein the multilayered hardmask structure further comprises a patterned etch stop hardmask layer positioned between the patterned halogen barrier hardmask layer and the patterned upper hardmask layer.

3. The semiconductor structure of claim 2 , wherein the patterned upper hardmask layer has a seam located therein.

4. The semiconductor structure of claim 1 , wherein the patterned halogen barrier hardmask layer includes a dopant, and is in direct physical contact with the patterned upper hardmask layer.

5. The semiconductor structure of claim 1 , wherein the patterned halogen barrier hardmask layer includes a fine grain structure, and is in direct physical contact with the patterned upper hardmask layer.

6. The semiconductor structure of claim 1 , further comprising a dielectric capping layer surrounding the conductive landing pad and on a surface of the first interconnect dielectric material layer.

7. The semiconductor structure of claim 1 , wherein the patterned upper hardmask layer is composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, or Al, and the patterned halogen barrier hardmask layer is composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, or Al, with the proviso that the patterned upper hardmask layer is compositionally different from the patterned halogen barrier hardmask layer.

8. A semiconductor structure comprising:
a first electrically conductive structure embedded in a first interconnect dielectric material layer and located in a magnetoresistive random access memory (MRAM) device area;
a conductive landing pad located on a surface of the first electrically conductive structure in the MRAM device area;
a magnetic tunnel junction (MTJ) structure located on the conductive landing pad;
a MTJ cap located on the MTJ structure;
a multilayered hardmask structure located on the MTJ cap, the multilayered hardmask structure comprising a patterned halogen barrier hardmask layer, a patterned upper hardmask layer and a patterned etch stop hardmask layer positioned between the patterned halogen barrier hardmask layer and the patterned upper hardmask layer, wherein the patterned upper hardmask layer has a seam located therein; and
a second interconnect dielectric material layer located above the first interconnect dielectric material layer and surrounding the MTJ structure, the MTJ cap and the multilayered hardmask structure, wherein a second electrically conductive structure is embedded in the second interconnect dielectric material layer and is in contact with an upper portion of the patterned upper hardmask layer.

9. The semiconductor structure of claim 8 , further comprising a dielectric capping layer surrounding the conductive landing pad and on a surface of the first interconnect dielectric material layer.

10. The semiconductor structure of claim 8 , wherein the patterned upper hardmask layer is composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, or Al, and the patterned halogen barrier hardmask layer is composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, or Al, with the proviso that the patterned upper hardmask layer is compositionally different from the patterned halogen barrier hardmask layer.

Assignees

• IBM

Inventors

• Rizzolo Michael
• Edelstein Daniel C
• Standaert Theodorus E
• Chung Kisup
• Chu Isabel C
• Arnold John C

Classifications

• H01L27/222

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title