Isolated circuit formed during back end of line process

Patent metadata

Field	Value
Publication number	US-10679986-B2
Application number	US-201816208335-A
Country	US
Kind code	B2
Filing date	Dec 3, 2018
Priority date	Aug 12, 2016
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

First claim

What is claimed is:

1. An apparatus comprising:
a first circuit formed on a semiconductor die, wherein the first circuit comprises a driver circuit configured to generate a drive signal for an external device that is not formed on the semiconductor die;
a second circuit formed on the same semiconductor die as the first circuit, the second circuit generating a first signal and the first circuit receiving the first signal via a galvanic isolation device, wherein the first circuit is configured to generate the drive signal in response to the first signal, and wherein the second circuit comprises a PWM controller, and wherein the first signal comprises a PWM signal;
wherein the first circuit is coupled to a first ground;
wherein the second circuit is coupled to a second ground;
wherein the first and second grounds are at different potentials; and
wherein the first circuit comprises a transistor comprising InGaZnO.

2. The apparatus of claim 1 wherein the first and second circuits are direct current (DC) isolated.

3. The apparatus of claim 1 , wherein the first ground is external to the semiconductor die.

4. The apparatus of claim 3 , wherein the second ground is external to the semiconductor die.

5. The apparatus of claim 1 , wherein the second ground is external to the semiconductor die.

6. The apparatus of claim 1 , wherein the external device comprises power transistors for a voltage converter, and wherein the PWM signal controls an output voltage of the voltage converter.

7. The apparatus of claim 6 , wherein the drive circuit is configured to generate the drive signal in accordance with an on time of the PWM signal.

8. The apparatus of claim 1 , wherein the driver circuit comprises a half bridge driver.

9. A method comprising:
forming a first circuit on a semiconductor die;
configuring the first circuit for generating a drive signal for an external device that is not formed on the semiconductor die;
forming a second circuit on the same semiconductor die as the first circuit, wherein the second circuit is configured to generate a first signal and the first circuit is configured to receive the first signal via a galvanic isolation device;
further configuring the first circuit for generating the drive signal in response to the first signal;
coupling the first circuit to a first ground;
coupling the second circuit to a second ground;
wherein the first and second grounds are at different potentials; and
wherein the first circuit comprises a half bridge driver.

10. The method of claim 9 , wherein forming the second circuit comprises forming a plurality of second devices that were formed during a front end of line (FEOL) portion of a process for manufacturing the semiconductor die, and;
wherein forming the first circuit comprises forming a plurality of first devices that were formed during a back end of line (BEOL) portion of the process of manufacturing the semiconductor die.

11. The method of claim 10 , wherein the first circuit does not include devices that were formed during the FEOL portion of the process for manufacturing the semiconductor die.

12. The method of claim 10 , further comprising forming an electrical isolation layer between the first and second circuits, wherein the electrical isolation layer is formed during the BEOL process.

13. The method of claim 10 wherein the plurality of first devices comprises a first thin film transistor (TFT).

14. The method of claim 10 further comprising:
forming a third circuit formed on the semiconductor die;
wherein the third circuit is DC isolated from the first and second circuits;
wherein the third circuit comprises a third conductor that is configured for electrical connection to a third ground that is external to the semiconductor die;
wherein the third circuit comprises a plurality of third devices that are formed during the BEOL process.

15. The method of claim 9 wherein the galvanic isolation device is external to the semiconductor die.

16. A method comprising:
forming a first circuit on a semiconductor die;
forming a second circuit on the semiconductor die, wherein the second circuit is configured to generate a first signal and the first circuit is configured to receive the first signal via a galvanic isolation device;
coupling the first circuit to a first ground;
coupling the second circuit to a second ground;
wherein the first and second grounds are at different potentials;
coupling first and second transistors, which are external to the semiconductor die, in series between a voltage input and the first ground; and
configuring the first circuit to generate first and second control signals for controlling the first and second transistors, respectively, in response to the first signal generated by the second circuit.

Assignees

• Renesas Electronics America Inc

Inventors

• Yoshida Kenji
• Sato Tetsuo
• Maeta Shigeru
• Kimura Toshio

Classifications

• H01L27/1207

  Electricity · mapped topic

• H01L21/8258

  Electricity · mapped topic

• H01L29/78603

  Electricity · mapped topic

• H01L25/0657

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic