Solid-state wafer bonding of functional materials on substrates and self-aligned contacts

Patent metadata

Field	Value
Publication number	US-10679964-B2
Application number	US-201515521886-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Nov 4, 2014
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.

First claim

The invention claimed is:

1. A method for integrating III-V semiconductor materials onto a rigid host substrate comprising:
depositing a separation layer of a metal film on the rigid host substrate, wherein the separation layer is unreactive with III-V semiconductor material;
depositing a thin layer of reactive metal on the separation layer;
bringing functional III-V semiconductor material into contact with the thin layer of reactive metal, wherein the separation layer provides a gap between the functional III-V semiconductor material and the host substrate such that the functional III-V semiconductor material is spaced from the host substrate; and
bonding by a low temperature heat treatment under a compressive pressure, wherein the thin layer of reactive metal and the functional semiconductor material are selected to undergo solid-state reaction and form a stable alloy under the low temperature heat treatment.

2. The method of claim 1 , wherein the thin layer of reactive metal comprises a patterned metal film.

3. The method of claim 2 , wherein the patterned metal film is recessed into a dielectric layer that is on top of the rigid host substrate.

4. The method of claim 2 , further comprising a separation metal layer that is unreactive with the III-V semiconductor material under the low temperature heat treatment and separates the reactive metal from the rigid substrate.

5. The method of claim 4 , wherein the III-V semiconductor material comprises an Arsenide or Phosphide III-V material and the reactive metal comprises Ni or Pd.

6. The method of claim 5 , wherein the separation metal layer comprises Cr, Ti, or W.

7. The method of claim 2 , further comprising a separation dielectric layer that is unreactive with the III-V semiconductor material under the low temperature heat treatment and separates the reactive metal from the rigid substrate.

8. The method of claim 7 , wherein the III-V semiconductor material comprises an Arsenide or Phosphide III-V material and the reactive metal comprises Ni or Pd.

9. The method of claim 8 , wherein the separation dielectric layer comprises Al 2 O 3 , SiO 2 , or Si 3 N 4 .

10. The method of claim 1 , wherein the III-V semiconductor material comprises an Arsenide or Phosphide III-V material and the reactive metal comprises Ni or Pd.

11. The method of claim 10 , wherein the separation layer comprises Cr, Ti, or W.

12. The method of claim 2 , further comprising a separation dielectric layer that is unreactive with the III-V semiconductor material under the low temperature heat treatment and separates the reactive metal from the rigid substrate.

13. The method of claim 12 , wherein the III-V semiconductor material comprises an Arsenide or Phosphide III-V material and the reactive metal comprises Ni or Pd.

14. The method of claim 8 , wherein the separation dielectric layer comprises Al 2 O 3 , SiO 2 , or Si 3 N 4 .

15. The method of claim 1 , wherein the III-V semiconductor material comprises an Arsenide or Phosphide III-V material and the reactive metal comprises Ni or Pd.

16. The method of claim 1 , wherein the thin layer of reactive metal comprises Ni or Pd and the III-V semiconductor material comprises an arsenide or phosphide III-V material.

17. The method of claim 1 , wherein the rigid host substrate comprises silicon, glass, or sapphire.

18. The method of claim 1 , wherein the low temperature is in the range of 220-300° C.

19. The method of claim 18 , wherein the heat treatment comprises treatment in a thermal furnace or a vacuum chamber flowing with forming gas.

20. The method of claim 19 , wherein the forming gas comprises N 2 or Ar.

21. The method of claim 1 , wherein the low temperature is high enough for the solid state reaction and low enough to avoid degradation of the functional semiconductor and the rigid substrate.

22. The method of claim 1 , further comprising a step of thinning the functional III-V semiconductor material to a predetermined thickness after said bonding.

23. The method of claim 22 , wherein the thinning comprises lapping, polishing, smart ion cut, or selective dry or wet etching.

24. The method of claim 1 , wherein the reactive metal is metal layer having a thickness that is equal to or less than half of the thickness of the III-V semiconductor material during the solid-state reaction.

25. The method of claim 1 , wherein the III-V semiconductor material comprises bulk III-V material.

26. The method of claim 25 , further comprising a thin film III-V epitaxial material on the bulk III-V material.

Assignees

• Univ California

Inventors

• Dayeh Shadi A
• Chen Renjie

Classifications

• H01L27/0605

  Electricity · mapped topic

• H01L21/8258

  Electricity · mapped topic

• H01L2224/29164

  Electricity · mapped topic

• H01L21/28575

  Electricity · mapped topic

• H01L2924/05432

  Electricity · mapped topic