Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10679903-B2
Application number	US-201815859775-A
Country	US
Kind code	B2
Filing date	Jan 2, 2018
Priority date	Dec 4, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
forming a fin-shaped structure on a substrate;
forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;
transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate;
removing part of the first metal gate and part of the second metal gate to form a first recess and a second recess;
forming a hard mask in the first recess and the second recess and on the ILD layer, wherein the hard mask contacts the first metal gate, the second metal gate, and the ILD layer directly;
removing part of the hard mask over the second metal gate to form a first trench exposing a surface of the second metal gate;
using the hard mask as a mask to remove the second metal gate and part of the fin-shaped structure from the first trench to form a second trench while the hard mask is disposed on the ILD layer; and
forming a dielectric layer into the second trench to form a single diffusion break (SDB) structure.

2. The method of claim 1 , further comprising:
forming a first spacer around the first gate structure and a second spacer around the second gate structure;
forming a contact etch stop layer (CESL) around the first spacer and the second spacer;
forming the ILD layer on the CESL;
removing part of the first metal gate and part of the second metal gate to form a first recess and a second recess;
forming the hard mask in the first recess and in the second recess.

3. The method of claim 2 , further comprising removing part of the second spacer to form the first trench.

4. The method of claim 2 , further comprising removing part of the CESL and part of the second spacer to form the first trench.

5. The method of claim 1 , further comprising forming a liner in the second trench before forming the dielectric layer.

6. The method of claim 5 , wherein the liner and the dielectric layer comprise different material.

7. The method of claim 5 , further comprising planarizing part of the dielectric layer, part of the liner, and part of the hard mask so that the top surfaces of the SDB structure and the hard mask are coplanar.

8. The method of claim 1 , further comprising forming the dielectric layer into the second trench to form the SDB structure while forming an air gap in the SDB structure.

9. The method of claim 1 , wherein the hard mask is made of a single material.

10. The method of claim 1 , wherein the hard mask comprises a single-layered structure.

11. The method of claim 1 , further comprising:
forming a patterned mask on the hard mask; and
using the patterned mask to remove part of the hard mask over the second metal gate to form the first trench.

12. The method of claim 1 , wherein the first trench exposes a sidewall of the ILD layer.

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching-Ling
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H01L21/823481 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic