Error reducing matrix generation

Patent metadata

Field	Value
Publication number	US-10679718-B2
Application number	US-201715725255-A
Country	US
Kind code	B2
Filing date	Oct 4, 2017
Priority date	Oct 4, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

First claim

What is claimed is:

1. An apparatus comprising:
a failure detection circuit that detects a failure of a decoding operation used to decode encoded data stored in a set of memory cells;
a test circuit that performs a test on the set of memory cells in response to the failure detection circuit detecting the failure;
a masking circuit that determines a masking array based on the test performed on the set of memory cells, wherein the masking array comprises an error location matrix determined based on the test performed on the set of memory cells, the error location matrix indicates memory cells in the set of memory cells having errors, and the error location matrix is stored; and
a decoding circuit that decodes the encoded data from the set of memory cells and during decoding ignores data from the memory cells indicated by the masking array.

2. The apparatus of claim 1 , wherein the test comprises one or more of a read operation, a program operation, a write operation, and a verify operation.

3. The apparatus of claim 1 , wherein performing the test comprises:
performing a write operation on the set of memory cells to write test data to each memory cell of the set of memory cells;
performing a read operation on each memory cell of the set of memory cells to obtain test result data; and
indicating an error for each memory cell of the set of memory cells in which the test data written to the memory cell does not match the test result data for the memory cell.

4. The apparatus of claim 3 , wherein the test data comprises one or more of user data, an inverse of the user data, and a predetermined test data pattern being written to the set of memory cells in response to the write operation.

5. The apparatus of claim 4 , wherein the test data comprises user data and the user data is already stored by the set of memory cells prior to the write operation, and the write operation overwrites the already stored user data as part of the test on the set of memory cells, the set of memory cells comprising write-in-place memory cells.

6. The apparatus of claim 3 , wherein the masking array is formed based on the error indication for each memory cell of the set of memory cells in which the test data written to the memory cell does not match the test result data for the memory cell.

7. The apparatus of claim 1 , wherein the masking array is used to form wired erasure pointers that indicate to the decoding circuit a likelihood of erroneous data.

8. The apparatus of claim 1 , wherein the masking circuit uses the masking array to mask the encoded data resulting in masked encoded data.

9. The apparatus of claim 8 , wherein the decoding circuit decodes the masked encoded data.

10. The apparatus of claim 8 , wherein the masking array masks the encoded data by using a logic function to set bits corresponding to the masking array to a same logic value.

11. The apparatus of claim 1 , further comprising a redundancy circuit that compares a number of error bits indicated by the masking array to a minimum threshold and a maximum threshold.

12. The apparatus of claim 11 , wherein the redundancy circuit accesses a redundancy storage in response to the number of error bits being greater than the maximum threshold.

13. A system comprising: a controller; and an array of storage locations, wherein the controller, in response to a failure detection circuit detecting a failure to decode undecoded data stored on the array of storage locations, is configured to: write test data to each storage location of the array of storage locations; read test result data stored on each storage location of the array of storage locations; compare the test data written to each storage location with the test result data read from each storage location; form an error location matrix based on the comparison between the test data written to each storage location and the test result data read from each storage location, wherein the error location matrix indicates storage locations in the array of storage locations having errors; store the error location matrix; and initiate performance of a decoding operation that ignores data from the storage locations indicated by the error location matrix during the decoding operation.

14. The system of claim 13 , wherein the controller is configured to initiate performance of the decoding operation in response to the error location matrix indicating a number of errors greater than a minimum threshold and less than a maximum threshold.

15. The system of claim 13 , wherein the error location matrix comprises hardwired erasure pointers provided to a decoder that performs a decoding operation on the undecoded data.

16. The system of claim 13 , wherein the controller is configured to perform an exclusive or (XOR) operation between the error location matrix and the undecoded data, and provide a result of the XOR operation to a decoder that performs a decoding operation on the result.

17. An apparatus comprising:
means for testing operation of a memory block in response to a failure detection circuit detecting a failure to decode data of the memory block during a decoding operation;
means for determining portions of the memory block that caused the failure to decode the data of the memory block during the decoding operation;
means for storing information indicating the determined portions of the memory block that caused the failure in an error location matrix, wherein the error location matrix is determined based on a comparison between test data written to memory locations of the memory block and test result data read from each storage location, and the error location matrix indicates memory locations in the memory block having errors; and
means for decoding the data of the memory block by ignoring data from the determined portions of the memory block that caused the failure during decoding.

Assignees

• Western Digital Tech Inc

Inventors

• Ghaly Mai
• Mishra Chandan
• Gholamipour Amir Hossein
• Zhang Yuheng
• Yee Lee Jeffrey Koon
• Hart James
• Helmick Daniel

Classifications

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title