Method, apparatus and system for handling data error events with a memory controller

Patent metadata

Field	Value
Publication number	US-2016004587-A1
Application number	US-201414428338-A
Country	US
Kind code	A1
Filing date	Apr 16, 2014
Priority date	Apr 16, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

First claim

What is claimed is:

1 . A memory controller comprising:
scrubber logic comprising circuitry to perform a first patrol scrub of a plurality of active segments of a memory, and to perform a second patrol scrub of one or more segments of the platform while the one or more segments are each available as a spare segment for the plurality of active segments; and sparer logic comprising circuitry to receive an indication of a first uncorrectable error event detected based on the first patrol scrub, wherein, of a first handler process and a second handler process, the sparer logic to signal only the first handler process in response to the indication of the first uncorrectable error event, the sparer logic further to receive an indication of a second uncorrectable error event detected based on the second patrol scrub, wherein, of the first handler process and the second handler process, the sparer logic to signal only the second handler process in response to the indication of the second uncorrectable error event.

2 . The memory controller of claim 1 , wherein the first handler process includes a machine check exception handler.

3 . The memory controller of claim 1 , wherein the second handler process includes an interrupt handler.

4 . The memory controller of claim 1 , wherein the second handler process registers a service request to replace a memory device.

5 . The memory controller of claim 1 , wherein the first handler process is executed during execution of a host operating system by a processor, and wherein the second handler process is executed during a system management mode of the processor.

6 . The memory controller of claim 1 , the sparer logic further to signal a handler process other than the first process if a threshold correctable error event is detected based on the first patrol scrub, wherein any handler process signaled in response to the threshold correctable error event is a handler process other than the first handler process.

7 . The memory controller of claim 6 , wherein the sparer logic to signal the handler process other than the first process includes the sparer logic to signal a handler process executed during a system management mode of a processor.

8 . A method comprising:
performing first patrol scrubbing of a plurality of active segments of a memory; if an uncorrectable error event is detected based on the first patrol scrubbing, then signaling a first handler process, wherein, of the first handler process and a second handler process, only the first handler process is signaled in response to the uncorrectable error event detected by the first patrol scrubbing; performing second patrol scrubbing of one or more segments of the memory while the one or more segments are each available as a spare segment for the plurality of active segments; and if an uncorrectable error event is detected based on the second patrol scrubbing, then signaling the second handler process, wherein, of the first handler process and a second handler process, only the first handler process is signaled in response to the uncorrectable error event detected by the first patrol scrubbing.

9 . The method of claim 8 , wherein the first handler process includes a machine check exception handler.

10 . The method of claim 8 , wherein the second handler process includes an interrupt handler.

11 . The method of claim 8 , wherein the second handler process registers a service request to replace a memory device.

12 . The method of claim 8 , wherein the first handler process is executed during execution of a host operating system by a processor, and wherein the second handler process is executed during a system management mode of the processor.

13 . The method of claim 8 , further comprising:
if a threshold correctable error event is detected based on the first patrol scrubbing, then signaling a handler process other than the first process, wherein any handler process signaled in response to the threshold correctable error event is a handler process other than the first handler process.

14 . The method of claim 13 , wherein signaling the handler process other than the first process includes signaling a handler process executed during a system management mode of a processor.

15 . A system comprising:
one or more memory devices; an interconnect; and a memory controller coupled to the one or more memory devices via the interconnect, the memory controller to control the one or more memory devices, the memory controller including:
scrubber logic comprising circuitry to perform first patrol scrubbing of a plurality of active segments of the one or more memory devices, and to perform second patrol scrubbing of one or more segments of the the one or more memory devices while the one or more segments are each available as a spare segment for the plurality of active segments; and
sparer logic comprising circuitry to receive an indication of a first uncorrectable error event detected based on the first patrol scrubbing, wherein, of a first handler process and a second handler process, the sparer logic to signal only the first handler process in response to the indication of the first uncorrectable error event, the sparer logic further to receive an indication of a second uncorrectable error event detected based on the second patrol scrubbing, wherein, of the first handler process and the second handler process, the sparer logic to signal only the second handler process in response to the indication of the second uncorrectable error event.

16 . The system of claim 15 , wherein the first handler process includes a machine check exception handler.

17 . The system of claim 15 , wherein the second handler process includes an interrupt handler.

18 . The system of claim 15 , wherein the second handler process registers a service request to replace a memory device.

19 . The system of claim 15 , wherein the first handler process is executed during execution of a host operating system by a processor, and wherein the second handler process is executed during a system management mode of the processor.

20 . The system of claim 15 , the sparer logic further to signal a handler process other than the first process if a threshold correctable error event is detected based on the first scrub, wherein any handler process signaled in response to the threshold correctable error event is a handler process other than the first handler process.

21 . A computer-readable storage medium having stored thereon instructions which, when executed by one or more processing units, cause the one or more processing units to perform a method comprising:
performing first patrol scrubbing of a plurality of active segments of a memory; if an uncorrectable error event is detected based on the first patrol scrubbing, then signaling a first handler process, wherein, of the first handler process and a second handler process, only the first handler process is signaled in response to the uncorrectable error event detected by the first patrol scrubbing; performing second patrol scrubbing of one or more segments of the memory while the one or more segments are each available as a spare segment for the plurality of active segments; and if an uncorrectable error event is detected based on the second patrol scrubbing, then signaling the second handler process, wherein, of the first handler process and a second handler process, only the first handler process is signaled in response to the uncorrectable error event detected by the

Assignees

• Intel Corp

Inventors

• Agrawal Anil
• Muthiyalu Satish
• Chen Yingwen
• Ganesan Meera

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/2094

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G06F2201/81

  Threshold · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0754

  by exceeding limits · CPC title