Structure, method and system for measuring RIE lag depth

Patent metadata

Field	Value
Publication number	US-10677855-B2
Application number	US-201715699094-A
Country	US
Kind code	B2
Filing date	Sep 8, 2017
Priority date	Sep 8, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.

First claim

I claim:

1. A structure for measuring reactive ion etching (RIE) lag depth of a semiconductor device, comprising:
a first metal layer;
a dielectric cap layer on top of the first metal layer;
an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and
a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width;
wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth.

2. The structure of claim 1 , wherein the array comprises two or more sub-arrays, a first sub-array having metal wires of a first width and at least one subsequent sub-array having metal wires of a second, different width from the first width.

3. The structure of claim 1 , wherein the first width or the second width of the metal wires is 24 nanometers or less.

4. The structure of claim 1 , wherein the first and second metal layers comprise at least one of a low dielectric constant (low-k) material and an ultra-low dielectric constant (ultra-low k) material.

5. The structure of claim 1 , wherein the dielectric cap layer comprises at least one of silicon nitride, silicon carbide, boron nitride, silicon boron nitride, silicon boron nitride carbon, silicon carbon nitride, carbon boron nitride, aluminum oxide, aluminum nitride, or carbon doped silicon nitride.

6. The structure of claim 1 , wherein the metal wires and the electrical ground element each comprise copper, ruthenium, cobalt, tungsten, titanium, aluminum or molybdenum.

7. The structure of claim 1 , wherein the electrical ground element is in the form of a plate, a comb or a serpentine element.

8. The structure of claim 1 , wherein one electrical ground element is in electrical contact with all sub-arrays.

9. The structure of claim 1 , wherein one electrical ground element is in electrical contact with a given sub-array.

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V

Classifications

• H01L23/53257

  Electricity · mapped topic

• H01L23/53228

  Electricity · mapped topic

• H01L22/12

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title