System and method for regulating transfer characteristics of integral analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10673448-B2
Application number	US-201716343785-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Nov 30, 2016
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate. Compared with the existing polyline mode, the present disclosure has better linearity; and it can be easily extended to cascade multistage integrators.

First claim

What is claimed is:

1. A system for regulating transfer characteristics of an integral analog-to-digital converter, comprising:
a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP), wherein the N is a positive integer and larger than or equal to 2; in the cascade N-stage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N.

2. The system of claim 1 , wherein, each integrator comprises a resistor, a capacitor, an operational transconductance amplifier and a switch; wherein, for each integrator, the positive input end of the operational transconductance amplifier is connected to the common mode voltage (VCM); one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; the two ends of the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the adjacent integrator.

3. The system of claim 2 , wherein the number of the integrators is three.

4. The system of claim 1 , wherein the number of the integrators is three.

5. A method for regulating transfer characteristics of an integral analog-to-digital converter by using adjusting system of claim 1 , comprising:
forming the cascade N-stage integrator structure using N integrators;
connecting the input end of the first integrator with a voltage;
connecting the output end of the Nth integrator to an output node (VRAMP), and
connecting the output end of each integrator with the input end of the adjacent integrator, so that the voltage changes of the output of the Nth integrator, namely the output node VRAMP, is in direct proportion with time to the power of N.

6. The method of claim 5 , wherein, each integrator comprises a resistor, a capacitor, an operational transconductance amplifier and a switch; wherein for each integrator, the positive input end of the operational transconductance amplifier is connected to a voltage source (VCM), and one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, and the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; and the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the adjacent integrator.

Assignees

• Shanghai Ic R&D Ct Co Ltd
• Chengdu Image Design Tech Co Ltd

Inventors

• He Xuehong
• Pi Changming
• Yang Hailing

Classifications

• H03M1/52 Primary

  Input signal integrated with linear return to datum · CPC title

• H03M1/10

  Calibration or testing · CPC title

• H03M1/0612 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title