Acoustic resonator having integrated lateral feature and temperature compensation feature
US-2016182011-A1 · Jun 23, 2016 · US
US10673405B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10673405-B2 |
| Application number | US-201616328753-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 30, 2016 |
| Priority date | Sep 30, 2016 |
| Publication date | Jun 2, 2020 |
| Grant date | Jun 2, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices that include a bottom electrode formed of a two-dimensional electron gas (2DEG). The disclosed FBAR devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2DEG bottom electrode may be able to achieve similar or increased carrier transport as compared to an FBAR device having a bottom electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the FBAR device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit device, comprising: a first layer comprising a first single crystal III-N compound; a second layer comprising a second single crystal III-N compound on the first layer; an air cavity underneath at least a portion of the first layer; and a bottom electrode comprising metal and laterally adjacent to and in contact with sidewalls of the first layer, such that a top portion of the first layer is between portions of the bottom electrode; wherein a two-dimensional electron gas (2DEG) region is inducible in the first layer. 2. The device of claim 1 , wherein the first single crystal III-N compound comprises gallium and nitrogen, and the second single crystal III-N compound comprises aluminum and nitrogen. 3. The device of claim 1 further comprising a top electrode on the second layer. 4. The device of claim 3 , wherein the bottom electrode and the top electrode comprise tungsten or molybdenum. 5. The device of claim 1 further comprising a third layer comprising a third single crystal III-N compound under the first layer and adjacent to the air cavity. 6. The device of claim 5 , wherein the third layer comprises nitrogen and at least one of aluminum, indium, and gallium. 7. The device of claim 1 further comprising a substrate underneath the third layer, wherein the substrate comprises a single crystal silicon layer. 8. The device of claim 1 further comprising an insulation material positioned between the air cavity and the first layer. 9. A mobile computing system comprising the integrated circuit device of claim 1 . 10. An integrated circuit device comprising: a first layer comprising a first single crystal III-N compound; a second layer comprising a second single crystal III-N compound on the first layer; an air cavity underneath at least a portion of the first layer; an insulation material positioned between the air cavity and the first layer; a top electrode on the second layer; and a bottom electrode comprising metal and laterally adjacent to and in contact with sidewalls of the first layer, such that a top portion of the first layer is between portions of the bottom electrode; wherein a two-dimensional electron gas (2DEG) region is inducible in the first layer. 11. The device of claim 10 , wherein the first single crystal III-N compound is gallium nitride, and the second single crystal III-N compound is aluminum nitride. 12. The device of claim 10 , wherein the first single crystal III-N compound comprises gallium and nitrogen, and the second single crystal III-N compound comprises aluminum and nitrogen. 13. The device of claim 12 , wherein the bottom electrode and the top electrode comprise tungsten or molybdenum. 14. The device of claim 10 further comprising a third layer comprising a third single crystal III-N compound under the first layer and adjacent to the air cavity. 15. The device of claim 10 wherein the insulation material lines the air cavity. 16. The FBAR device of claim 10 , wherein the bottom electrode is on the insulation material, and at least part of the first layer is on the insulation material. 17. A mobile computing system comprising the integrated circuit device of claim 10 . 18. A method of producing a resonator device, the method comprising: depositing insulation material on a monocrystalline substrate; etching a trench in the insulation material to expose the underlying substrate; epitaxially depositing a first layer into the trench and so that the first layer laterally overflows onto an upper surface of the insulation material; epitaxially depositing at least part of a second layer on the first layer to provide a two-dimensional electron gas (2DEG) region in the first layer adjacent to the second layer; forming a bottom electrode laterally adjacent to and in contact with sidewalls of the first layer, such that a top portion of the first layer is between portions of the bottom electrode, the bottom electrode being on the insulation material and comprising metal; and forming an air cavity underneath at least a portion of the first layer. 19. The method of claim 18 further comprising forming a nucleation layer comprising a single crystal III-N material in the trench and on the substrate prior to depositing the first layer into the trench. 20. The method of claim 18 further comprising etching some of the insulation material to form the air cavity, wherein the bottom electrode is on a remaining portion of the insulation material, and at least part of the first layer is on the remaining portion of the insulation material.
Electricity · mapped topic
implemented with thin-film techniques · CPC title
for electromechanical delay lines or filters · CPC title
Electricity · mapped topic
the resonators or networks being of the air-gap type · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.