Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition

Patent metadata

Field	Value
Publication number	US-10672645-B2
Application number	US-201816106269-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Oct 31, 2013
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

First claim

What is claimed is:

1. A semiconductor on insulator structure comprising:
a single crystal silicon handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 Ohm-cm;
a multilayer in interfacial contact with the front surface layer, the multilayer comprising one or more passivated semiconductor layers, wherein the one or more passivated semiconductor layers comprise a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;
a semiconductor layer in interfacial contact with the multilayer, the semiconductor layer comprising a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;
a dielectric layer in interfacial contact with the semiconductor layer; and
a semiconductor device layer in interfacial contact with the dielectric layer.

2. The semiconductor on insulator structure of claim 1 wherein the single crystal silicon handle substrate further comprises a handle dielectric layer between the front surface of the single crystal silicon handle substrate and the multilayer.

3. The semiconductor on insulator structure of claim 2 wherein the handle dielectric layer comprises a layer selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof.

4. The semiconductor on insulator structure of claim 1 wherein the single crystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

5. The semiconductor on insulator structure of claim 1 wherein single crystal silicon handle substrate has a bulk resistivity between about 100 Ohm-cm and about 100,000 Ohm-cm.

6. The semiconductor on insulator structure of claim 1 wherein the single crystal silicon handle substrate has a bulk resistivity between about 750 ohm cm and about 10,000 Ohm-cm.

7. The semiconductor on insulator structure of claim 1 wherein the single crystal silicon handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

8. The semiconductor on insulator structure of claim 1 wherein single crystal silicon handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

9. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer comprises material selected from the group consisting of SiGe, SiC, and Ge.

10. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer has a thickness of between about 5 nanometers and about 1000 nanometers.

11. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer has a thickness of between about 20 nanometers and about 1000 nanometers.

12. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer has a thickness of between about 20 nanometers and about 500 nanometers.

13. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer has a resistivity at least about 1000 Ohm-cm.

14. The semiconductor on insulator structure of claim 1 wherein each passivated semiconductor layer has a resistivity at least about 3000 Ohm-cm.

15. The semiconductor on insulator structure of claim 1 wherein the total thickness of the multilayer comprising the one or more passivated semiconductor layers is between about 0.3 micrometers and about 5 micrometers.

16. The semiconductor on insulator structure of claim 1 wherein the total thickness of the multilayer comprising the one or more passivated semiconductor layers is between about 0.3 micrometers and about 3 micrometers.

17. The semiconductor on insulator structure of claim 1 wherein the total thickness of the multilayer comprising the one or more passivated semiconductor layers is between about 0.3 micrometers and about 2 micrometers.

18. The semiconductor on insulator structure of claim 1 wherein the total thickness of the multilayer comprising the one or more passivated semiconductor layers is between about 2 micrometers and about 3 micrometers.

19. The semiconductor on insulator structure of claim 1 wherein the dielectric layer in interfacial contact with the semiconductor layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

20. The semiconductor on insulator structure of claim 1 wherein semiconductor device layer in interfacial contact with the dielectric layer comprises single crystal silicon.

21. A semiconductor on insulator structure comprising:
a single crystal semiconductor handle wafer comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle wafer and the other of which is a back surface of the single crystal semiconductor handle wafer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle wafer, a bulk single crystal semiconductor region, and the central plane of the single crystal semiconductor handle wafer between the front and back surfaces of the single crystal semiconductor handle wafer, wherein the single crystal semiconductor handle wafer has a minimum bulk resistivity of at least 100 Ohm-cm;
a first semiconductor layer comprising a polycrystalline or an amorphous structure, wherein the first semiconductor layer comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;
a first passivating layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride;
a second semiconductor layer comprising a polycrystalline or an amorphous structure, wherein the second semiconductor layer comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;
a dielectric layer; and
a semiconductor device layer in interfacial contact with the dielectric layer.

22. The semiconductor on insulator structure of claim 21 further comprising a second passivating layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride.

23. The semiconductor on insulator structure of claim 21 wherein the single crystal silicon handle substrate further comprises a handle dielectric layer between the front surface of the single crystal silicon handle substrate and the multilayer.

24. The semiconductor on insulator structure of claim 23 wherein the handle dielectric layer comprises a layer selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof.

25. The semiconductor on insulator structure of claim 21 wherein the single crystal semiconductor handle wafer compris

Assignees

• Globalwafers Co Ltd

Inventors

• Peidous Igor
• Pellicano Illaria Katia Marianna

Classifications

• H01L21/76251 Primary

  Electricity · mapped topic

• H01L21/02532

  Electricity · mapped topic

• H01L21/02238

  Electricity · mapped topic

• H01L21/0262

  Electricity · mapped topic

• H01L21/02529

  Electricity · mapped topic