Integrated circuit tester probe contact liner

US10670653B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10670653-B2
Application numberUS-201815979853-A
CountryUS
Kind codeB2
Filing dateMay 15, 2018
Priority dateMay 15, 2018
Publication dateJun 2, 2020
Grant dateJun 2, 2020

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of testing an integrated circuit (IC) device, the method comprising: passing an incoming electrical current from a probe contact through a conductive glass matrix liner upon each exterior surface of the probe contact and through a solder bump upon an IC device contact to the IC device contact; receiving, with the probe contact, a return electrical current from the IC device contact through the solder bump and through the conductive glass matrix liner. 2. The method of claim 1 , wherein the IC device is a wafer. 3. The method of claim 1 , wherein the IC device is a die. 4. The method of claim 1 , wherein the conductive glass matrix liner comprises a matrix of a conductive polymer and glass. 5. The method of claim 1 , wherein the conductive glass matrix liner prevents material of the solder bump from adhering thereto. 6. A method of fabricating an integrated circuit (IC) device probe card, the method comprising: forming a conductive glass frit upon a probe contact and upon the IC device probe card; evaporating conductive glass frit upon the IC device probe card and retaining the conductive glass frit upon the probe contact; and locally thermally conditioning the conductive glass frit upon the probe contact to form a conductive glass matrix liner upon the probe contact. 7. The method of claim 6 , wherein thermally conditioning the conductive glass frit comprises: directing a laser beam to directly thermally condition the conductive glass frit upon the probe contact. 8. The method of claim 7 , wherein a central bisector axis of the laser beam is coincident with a central bisector axis of the probe contact. 9. The method of claim 7 , wherein a diameter of the laser beam is less than a diameter of the probe contact. 10. The method of claim 6 , wherein thermally conditioning the conductive glass frit comprises: directing a laser beam to the probe contact and indirectly thermally conditioning the conductive glass frit upon the probe contact by transferring heat from the probe contact to the conductive glass frit upon the probe contact. 11. The method of claim 6 , wherein the conductive glass matrix liner prevents material of a solder bump of an IC device contact from adhering thereto. 12. A method of fabricating an integrated circuit (IC) device probe card, the method comprising: forming a conductive glass frit upon a probe card and upon a probe contact; thermally conditioning the conductive glass frit so as to form a conductive glass matrix liner upon and nearest the probe contact so as to retain non-thermally conditioned conductive glass frit; removing the non-thermally conditioned conductive glass frit. 13. The method of claim 12 , wherein thermally conditioning the conductive glass frit comprises: directing a laser beam to directly thermally condition the conductive glass frit upon and nearest the probe contact. 14. The method of claim 13 , wherein a central bisector axis of the laser beam is coincident with a central bisector axis of the probe contact. 15. The method of claim 12 , wherein thermally conditioning the conductive glass frit comprises: directing a laser beam to the probe contact and indirectly thermally conditioning the conductive glass frit upon and nearest the probe contact by transferring heat from the probe contact to the conductive glass frit upon and nearest the probe contact. 16. The method of claim 12 , wherein the conductive glass matrix liner prevents material of a solder bump of an IC device contact from adhering thereto.

Assignees

Inventors

Classifications

  • of rectilinear seams · CPC title

  • Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

  • related to layers · CPC title

  • Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

  • related to tip portion · CPC title

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Frequently asked questions

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What does patent US10670653B2 cover?
An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by apply…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G01R31/2889. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).