Highly integrated high voltage actuator driver

Patent metadata

Field	Value
Publication number	US-10666145-B2
Application number	US-201816483075-A
Country	US
Kind code	B2
Filing date	Feb 2, 2018
Priority date	Feb 3, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A single die driver integrated circuit is coupled to an input portion having a single inductor receiving a low voltage source and configured to drive a capacitive load with an output voltage. The driver includes a bidirectional synchronous power converter stage configured to generate a switching voltage from the input portion at a switching node and to generate a high voltage waveform from the low-voltage source. An embedded controller is configured to control a switch of the power converter stage.

First claim

What is claimed is:

1. A single die driver integrated circuit (IC) ( 2020 , 2120 ) coupled to an input portion ( 2010 ) comprising a single inductor (L 1 ) receiving a low voltage source (VIN) and configured to drive a capacitive load ( 2090 ) with an output voltage (VOUT), the driver comprising:
a bidirectional synchronous power converter stage ( 2030 ) configured to generate a switching voltage VSW from the input portion at a switching node and generate a high voltage waveform VFOLDED from the low-voltage source; and
an embedded controller ( 2050 ) configured to control a switch of the power converter stage,
wherein the bidirectional synchronous power converter stage comprises a boost-buck converter configured to generate the high voltage waveform from the low-voltage source by transferring increments of energy to the load in a forward-boost mode and from the load in a reverse-buck mode.

2. The driver of claim 1 , wherein the bidirectional synchronous power converter stage is a two-switch converter.

3. The driver of claim 1 , further comprising a low frequency full-bridge stage ( 2040 ) comprising four switches (M 3-6 ) configured to receive and unfold the high voltage waveform to generate a full swing signal across the load.

4. The driver of claim 3 , wherein the low frequency full-bridge stage further comprises a first half bridge driver ( 2210 ) driving a first pair of the four switches (M 3-4 ) and a second half bridge driver ( 2220 ) driving a second pair of the four switches (M 5-6 ).

5. The driver of claim 4 , wherein the embedded controller is further configured to control the first half bridge driver and/or the second half bridge driver.

6. The driver of claim 3 , wherein the low frequency full-bridge stage is configured to operate over a frequency range of 300 Hz and below.

7. The driver of claim 2 , further comprising a low frequency full-bridge stage ( 2040 ) comprising four switches (M 3-6 ) configured to receive and unfold the high voltage waveform to generate a full swing signal across the load.

8. The driver of claim 7 , wherein the low frequency full-bridge stage further comprises a first half bridge driver ( 2210 ) driving a first pair of the four switches (M 3-4 ) and a second half bridge driver ( 2220 ) driving a second pair of the four switches (M 5-6 ).

9. The driver of claim 8 , wherein the embedded controller is further configured to control the first half bridge driver and/or the second half bridge driver.

10. The driver of claim 7 , wherein the low frequency full-bridge stage is configured to operate over a frequency range of 300 Hz and below.

11. A single die driver integrated circuit (IC) ( 2020 , 2120 ) coupled to an input portion ( 2010 ) comprising a single inductor (L 1 ) receiving a low voltage source (VIN) and configured to drive a capacitive load ( 2090 ) with an output voltage (VOUT), the driver comprising:
a bidirectional synchronous power converter stage ( 2030 ) configured to generate a switching voltage VSW from the input portion at a switching node and generate a high voltage waveform VFOLDED from the low-voltage source; and
an embedded controller ( 2050 ) configured to control a switch of the power converter stage,
wherein the input portion further comprises a filter capacitor (C FILTER ) connected across the low voltage source and the high voltage waveform, and a sense resistor (R 1 ) connected between the low voltage source and the single inductor, and the single inductor is connected between the sense resistor and a switching node of the power converter stage.

12. The driver of claim 11 , further comprising a low frequency full-bridge stage ( 2040 ) comprising four switches (M 3-6 ) configured to receive and unfold the high voltage waveform to generate a full swing signal across the load.

13. The driver of claim 12 , wherein the low frequency full-bridge stage further comprises a first half bridge driver ( 2210 ) driving a first pair of the four switches (M 3-4 ) and a second half bridge driver ( 2220 ) driving a second pair of the four switches (M 5-6 ).

14. The driver of claim 13 , wherein the embedded controller is further configured to control the first half bridge driver and/or the second half bridge driver.

15. A single die driver integrated circuit (IC) ( 2020 , 2120 ) coupled to an input portion ( 2010 ) comprising a single inductor (L 1 ) receiving a low voltage source (VIN) and configured to drive a capacitive load ( 2090 ) with an output voltage (VOUT), the driver comprising:
a bidirectional synchronous power converter stage ( 2030 ) configured to generate a switching voltage VSW from the input portion at a switching node and generate a high voltage waveform VFOLDED from the low-voltage source;
an embedded controller ( 2050 ) configured to control a switch of the power converter stage;
a current feedback sensor ( 2052 ) configured to detect bidirectional current at the input portion;
a zero voltage switching (ZVS) detector ( 2053 ) configured to detect a zero voltage condition for the switching node voltage V SW ;
a communication interface ( 2054 ) configured to receive an input from an external peripheral device and/or transmit to the external peripheral device; and
an analog-to-digital converter (ADC) ( 2055 ) configured to receive an output form a difference amplifier 2056 disposed between a V FOLDED node and a V IN node,
wherein the embedded controller is configured to receive a signal from at least one of the current feedback sensor, the ZVS detector, the communication interface, and the ADC.

16. The driver of claim 15 , further comprising a unidirectional power input stage ( 2110 ) shown in FIG. 6B comprising an active switch (M 9 ) and a comparator ( 2156 ), wherein the embedded controller is configured to receive a signal from the comparator.

17. The driver of claim 15 , wherein the DAC further comprises:
a first single ended n-bit hybrid digital-to-analog converter (DAC) ( 2610 ) switchably referenced to the input voltage and a supply voltage (V DD );
a second single ended n-bit hybrid digital-to-analog converter (DAC) ( 2620 ) switchably referenced to the input voltage and connected in series to the first DAC via a switch (SW series );
a comparator configured to receive a first output from the first DAC and a second output from the second DAC; and
a successive approximation register (SAR) ( 2650 ) configured to provide an n-bit output to the second DAC and a complement of the eight bit output to the first DAC,
wherein n is a positive integer and the first DAC and the second DAC are combined in a pseudo-differential bipolar manner.

18. The driver of claim 15 , wherein the embedded controller is configured to sense the voltage over the load and provide through the communication interface a state and/or voltage of the output in real-time.

19. The driver of claim 15 , wherein the embedded controller is configured to track a reference waveform received via the communication interface to control the bidirectional synchronous power converter stage and/or the full-bridge stage to produce the full swing signal according to the reference waveform.

20. The driver of claim 15 , further comprising a low frequency full-bridge stage ( 2040 ) comprising four switches (M 3-6 ) configured to receive and unfold the high voltage waveform to generate a full swing signal across the load.

Assignees

• Harvard College

Inventors

• Chaput Simon
• Wei Gu-Yeon

Classifications

• H02N1/006

  of the gap-closing type (H02N1/004 takes precedence) · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H02N2/065

  Large signal circuits, e.g. final stages · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M1/083

  for the ignition at the zero crossing of the voltage or the current · CPC title