Vertical bipolar transistors

Patent metadata

Field	Value
Publication number	US-10665702-B2
Application number	US-201816151511-A
Country	US
Kind code	B2
Filing date	Oct 4, 2018
Priority date	Dec 27, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.

First claim

What is claimed is:

1. A vertical bipolar transistor comprising:
a substrate including a first well of a first conductivity type and a second well of a second conductivity type, the second conductivity type being different from the first conductivity type, the first well adjoining the second well;
a first fin extending from the first well, the first fin including a first conductive region at a top portion thereof, the first conductive region having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor;
a second fin extending from the first well and spaced apart from the first fin, the second fin including a second conductive region at a top portion thereof, the second conductive region having the first conductivity type and configured to serve as a base of the vertical bipolar transistor;
a third fin extending from the second well, the third fin including a third conductive region at a top portion thereof, the third conductive region having the second conductivity type and configured to serve as a collector of the vertical bipolar transistor; and
a first sub-emitter region and a second sub-emitter region in the first well and at both sides of the first fin, the first sub-emitter region and the second sub-emitter region having the second conductivity type, the first sub-emitter region and the second sub-emitter region laterally spaced apart from each other, and the first sub-emitter region and the second sub-emitter region configured to function as the emitter together with the first conductive region.

2. The vertical bipolar transistor of claim 1 , further comprising:
a first isolation region in the first well and laterally between the first fin and the second fin, the first isolation region extending to a first depth in the first well, the first depth being shallower than a second depth of the first well.

3. The vertical bipolar transistor of claim 2 , further comprising:
a second isolation region at a boundary between the first well and the second well and laterally between the second fin and the third fin, the second isolation region extending to a third depth, the third depth being shallower than each of the first depth of the first well and a fourth depth of the second well.

4. The vertical bipolar transistor of claim 1 , further comprising:
a first isolation region at a boundary between the first well and the second well and laterally between the second fin and the third fin, the first isolation region extending to a first depth, the first depth being shallower than both a second depth of the first well and a third depth of the second well.

5. The vertical bipolar transistor of claim 1 , further comprising at least one of:
a first sub-base region and a second sub-base region in the first well and at both sides of the second fin, the first sub-base region and the second sub-base region having the first conductivity type, the first sub-base region and the second sub-base region laterally spaced apart from each other, and the first sub-base region and the second sub-base region configured to function as the base together with the second conductive region; or
a first sub-collector region and a second sub-collector region in the second well and at both sides of the third fin, the first sub-collector region and the second sub-collector region having the second conductivity type, the first sub-collector region and the second sub-collector region laterally spaced apart from each other, and the second sub-collector region configured to function as the collector together with the third conductive region.

6. The vertical bipolar transistor of claim 1 , wherein
the second conductive region has a shape surrounding the first conductive region in a plan view, and
the third conductive region has a shape surrounding the second conductive region in the plan view.

7. The vertical bipolar transistor of claim 6 , wherein the first conductive region has a disk shape or a rectangular shape in the plan view.

8. The vertical bipolar transistor of claim 1 , further comprising:
the first fin including a fourth conductive region, the fourth conductive region being a portion of the first fin under the first conductive region, and the fourth conductive region having the first conductivity type;
the second fin including a fifth conductive region, the fifth conductive region being a portion of the second fin under the second conductive region, and the fifth conductive region having the first conductivity type; and
the third fin including a sixth conductive region, the sixth conductive region being a portion of the third fin under the third conductive region, and the sixth conductive region having the second conductivity type.

9. A vertical bipolar transistor comprising:
a substrate including a first well of a first conductivity type and a second well of a second conductivity type, the second conductivity type being different from the first conductivity type, the first well adjoining the second well;
a first conductive region in the first well, the first conductive region having the second conductivity type, the first conductive region configured to serve as a emitter of the vertical bipolar transistor;
a first fin extending from the first well of the substrate, the first fin laterally spaced apart from the first conductive region, the first fin including a second conductive region at a top portion thereof, the second conductive region having the first conductivity type;
a second fin extending from the second well of the substrate, the second fin including a third conductive region at a top portion thereof, the third conductive region having the second conductivity type;
at least one sub-base region in the first well, the at least one sub-base region having the first conductivity type, the at least one sub-base region aligned with respect to the first fin and laterally spaced apart from the first conductive region, the second conductive region and the at least one sub-base region collectively configured to serve as a base of the vertical bipolar transistor; and
at least one sub-collector region in the second well, the at least one sub-collector region having the second conductivity type, the at least one sub-collector region aligned with respect to the second fin and laterally spaced apart from the at least one sub-base region, the third conductive region and the at least one sub-collector region collectively configured to serve as a collector of the vertical bipolar transistor.

10. The vertical bipolar transistor of claim 9 , wherein the at least one sub-base region includes a first sub-base region and a second sub-base region, and the first sub-base region and the second sub-base region are laterally on opposite sides of the first fin.

11. The vertical bipolar transistor of claim 10 , further comprising:
an isolation region in the first well and having a depth shallower than a depth of the first well, the isolation region being between the first conductive region and one of the first sub-base region and the second sub-base region that faces the first conductive region.

12. The vertical bipolar transistor of claim 10 , wherein the at least one sub-collector region includes a first sub-collector region and a second sub-collector region, and the first sub-collector region and the second sub-collector region are laterally on opposite sides of the second fin.

13. The vertical bipolar transistor of claim 12 , further comprising:
an isolation region is at a boundary between the first well and the second well and between (1) one of the first sub-base region and the second sub-base region and (2) one of the first sub-coll

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myung Gil
• Kang Ill Seo
• Park Yong Hee
• Baek Sang Hoon
• Cheon Keon Yong

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L27/0623

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/732 Primary

  Electricity · mapped topic