Data selector based on threshold voltage defined

Patent metadata

Field	Value
Publication number	US-10665553-B1
Application number	US-201916699124-A
Country	US
Kind code	B1
Filing date	Nov 29, 2019
Priority date	Nov 30, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

First claim

What is claimed is:

1. A data selector based on threshold voltage defined (TVD), comprising:
two AND gates;
an OR gate;
and three buffers;
wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic,
the AND gates and the OR gate each have a pre-charge control terminal, a discharge control terminal, an evaluation control terminal, a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, an output terminal, and an inverting output terminal,
the two AND gates are respectively referred to as a first AND gate and a second AND gate, and the three buffers are respectively referred to as a first buffer, a second buffer, and a third buffer,
the discharge control terminal of the first AND gate, the discharge control terminal of the second AND gate, and an input terminal of the first buffer are connected, and a connecting terminal of the discharge control terminal of the first AND gate, the discharge control terminal of the second AND gate, and the input terminal of the first buffer is a discharge control terminal of the data selector and allows a discharge control signal to be accessed therein,
the pre-charge control terminal of the first AND gate, the pre-charge control terminal of the second AND gate, and the input terminal of an second buffer are connected, and a connecting terminal of the pre-charge control terminal of the first AND gate, the pre-charge control terminal of the second AND gate, and the input terminal of the second buffer is a pre-charge control terminal of the data selector and allows a pre-charge control signal to be accessed therein,
the evaluation control terminal of the first AND gate, the evaluation control terminal of the second AND gate, and an input terminal of the third buffer are connected, and a connecting terminal of the evaluation control terminal of the first AND gate, the evaluation control terminal of the second AND gate, and the input terminal of the third buffer is an evaluation control terminal of the data selector and allows an evaluation control signal to be accessed therein,
an output terminal of the first buffer is connected to the discharge control terminal of the OR gate, an output terminal of the second buffer is connected to the pre-charge control terminal of the OR gate, and an output terminal of the third buffer is connected to the evaluation control terminal of the OR gate,
the first input terminal of the first AND gate is a first input terminal of the data selector and allows a first input signal to be accessed therein, the first inverting input terminal of the first AND gate is a first inverting input terminal of the data selector and allows an inversion signal of the first input signal to be accessed therein, the first input terminal of the second AND gate is a second input terminal of the data selector and allows a second input signal to be accessed therein, and the first inverting input terminal of the second AND gate is a second inverting input terminal of the data selector and allows an inversion signal of the second input signal to be accessed therein,
the second inverting input terminal of the first AND gate is connected to the second input terminal of the second AND gate, and a connecting terminal of the second inverting input terminal of the first AND gate and the second input terminal of the second AND gate is a selection terminal of the data selector and allows a selection signal to be accessed therein,
the second input terminal of the first AND gate is connected to the second inverting input terminal of the second AND gate, and a connecting terminal of the second input terminal of the first AND gate and the second inverting input terminal of the second AND gate is an inverting selection terminal of the data selector and allows an inversion signal of the selection signal to be accessed therein,
the output terminal of the first AND gate is connected to the first input terminal of the OR gate, the inverting output terminal of the first AND gate is connected to the first inverting input terminal of the OR gate, the output terminal of the second AND gate is connected to the second input terminal of the OR gate, and the inverting output terminal of the second AND gate is connected to the second inverting input terminal of the OR gate,
and the output terminal of the OR gate is an output terminal of the selector, and the inverting output terminal of the OR gate is an inverting output terminal of the selector.

2. A data selector based on TVD according to claim 1 ,
wherein each AND gate comprises: a first PMOS transistor; a second PMOS transistor; a third PMOS transistor; a fourth PMOS transistor; a fifth PMOS transistor; a first NMOS transistor; a second NMOS transistor; a third NMOS transistor; a fourth NMOS transistor; a fifth NMOS transistor; a sixth NMOS transistor; a seventh NMOS transistor; an eighth NMOS transistor; a ninth NMOS transistor; a tenth NMOS transistor; an eleventh NMOS transistor; a twelfth NMOS transistor; a thirteenth NMOS transistor; a fourteenth NMOS transistor; a fifteenth NMOS transistor; a sixteenth NMOS transistor; a seventeenth NMOS transistor; an eighteenth NMOS transistor; a nineteenth NMOS transistor; a twentieth NMOS transistor; and a twenty-first NMOS transistor,
wherein a source of the first PMOS transistor is accessed to a power supply,
a gate of the first PMOS transistor, a gate of the first NMOS transistor, and a gate of the fourth NMOS transistor are connected, and a connecting terminal of the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the gate of the fourth NMOS transistor is the discharge control terminal of the AND gate,
a drain of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth PMOS transistor, and a source of the fifth PMOS transistor are connected,
a gate of the second PMOS transistor is connected to a gate of the fifth PMOS transistor, and a connecting terminal of the gate of the second PMOS transistor and the gate of the fifth PMOS transistor is the pre-charge control terminal of the AND gate,
a drain of the second PMOS transistor, a drain of the third PMOS transistor, a drain of the first NMOS transistor, a drain of the second NMOS transistor, a gate of the fourth PMOS transistor, and a gate of the third NMOS transistor are connected, and a connecting terminal of the drain of the second PMOS transistor, the drain of the third PMOS transistor, the drain of the first NMOS transistor, the drain of the second NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the third NMOS transistor is the output terminal of the AND gate,
a gate of the third PMOS transistor, a gate of the second NMOS transistor, a drain of the fourth PMOS transistor, a drain of the third NMOS transistor, a drain of the fifth PMOS transistor, and a drain of the fourth NMOS transistor are connected, and a connecting terminal of the gate of the third PMOS transistor, the gate of the second NMOS transistor, the drain of the fourth PMOS transistor, the drain of the third NMOS transistor, the drain of the fifth PMOS transistor, and a drain of the fourth NMOS transistor is the inverting output terminal of the AND gate,
a source of the first NMOS transistor is grounded, a source of the second NMOS transistor, a drain of the fifth NMOS transistor, a drain of the sixth NMOS transistor, a drain of the seventh NMOS transistor, and a drain of the eighth NMOS transistor are connected, a source of the third NMOS transistor, a drain of the ninth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, and a drain of the twelfth NMOS transistor are connected, and a source of the fourth NMOS transistor is grounded,
a gate of the fifth NMOS transisto

Assignees

• Univ Ningbo

Inventors

• Wang Pengjun
• Li Liwei
• Zhang Yuejun
• Chen Bo
• Li Gang

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H01L23/576 Primary

  Electricity · mapped topic

• H10W42/405 Primary

  using active circuits · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title