Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors

Patent metadata

Field	Value
Publication number	US-10164768-B1
Application number	US-201815904222-A
Country	US
Kind code	B1
Filing date	Feb 23, 2018
Priority date	Feb 23, 2018
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

First claim

What is claimed is:

1. A circuit comprising:
a dynamic differential logic gate having first and second outputs; and
a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate;
wherein the dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal; and
wherein the first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

2. The circuit of claim 1 , wherein the first preset value and the second preset value have opposite logic values.

3. The circuit of claim 1 , wherein the first dynamic differential logic gate comprises a dynamic differential exclusive-or (XOR) gate.

4. The circuit of claim 1 , wherein, during a second phase of the clock signal, the dynamic differential logic gate is configured to:
perform a first differential logic function on input data bits to generate a first pair of complementary data bits; and
output the first pair of complementary data bits at the first and second outputs of the dynamic differential logic gate.

5. The circuit of claim 4 , wherein the first static differential logic gate is configured to:
perform a second differential logic function on at least the first pair of complementary data bits to generate a second pair of complementary data bits; and
output the second pair of complementary data bits at the first and second outputs of the first static differential logic gate.

6. The circuit of claim 5 , wherein the clock signal is low during the first phase of the clock signal, and high during the second phase of the clock signal.

7. The circuit of claim 5 , wherein the clock signal is high during the first phase of the clock signal, and low during the second phase of the clock signal.

8. The circuit of claim 5 , further comprising:
a second static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the first static differential logic gate;
wherein the second static differential logic gate is configured to preset both the first and second outputs of the second static differential logic gate to the first preset value when the second preset value is input to both the first and second inputs of the second static differential logic gate.

9. The circuit of claim 8 , wherein the first preset value and the second preset value have opposite logic values.

10. The circuit of claim 5 , wherein the first differential logic function is a differential exclusive-or (XOR) function.

11. A processor comprising:
a first differential latch configured to latch first complementary data, and to output the latched first complementary data; and
a first pipeline configured to perform first operations on the latched first complementary data to generate second complementary data;
wherein the first pipeline comprises one or more dynamic differential logic gates in a first stage of the first pipeline, and one or more static differential logic gates in a second stage of the first pipeline; and
wherein each of the one or more dynamic differential logic gates in the first stage is configured to receive a clock signal and to preset respective outputs to a first preset value during a first phase of the clock signal.

12. The processor of claim 11 , wherein each of the one or more static differential logic gates in the second stage is configured to preset respective outputs to a second preset value when the outputs of the one or more dynamic differential logic gates in the first stage are preset to the first preset value.

13. The processor of claim 12 , wherein the first preset value and the second preset value have opposite logic values.

14. The processor of claim 13 , wherein:
the first pipeline comprises one or more static differential logic gates in a third stage of the first pipeline; and
each of the one or more static differential logic gates in the third stage is configured to preset respective outputs to the first preset value when the outputs of the one or more static differential logic gates in the second stage are preset to the second preset value.

15. The processor of claim 12 , wherein the first differential latch is configured to output the latched first complementary data to the first pipeline during a second phase of the clock signal.

16. The processor of claim 15 , wherein the clock signal is low during the first phase of the clock signal and high during the second phase of the clock signal.

17. The processor of claim 11 , further comprising:
a second differential latch configured to latch the second complementary data, and to output the latched second complementary data; and
a second pipeline configured to perform second operations on the latched second complementary data to generate third complementary data.

18. The processor of claim 17 , wherein:
the first differential latch is configured to output the latched first complementary data to the first pipeline during a second phase of the clock signal; and
the second differential latch is configured to output the latched second complementary data to the second pipeline during the first phase of the clock signal.

19. The processor of claim 18 , wherein the clock signal is low during the first phase of the clock signal and the clock signal is high during the second phase of the clock signal.

20. The processor of claim 18 , wherein the second pipeline comprises one or more static differential logic gates in a first stage of the second pipeline.

21. The processor of claim 17 , wherein:
the first operations include mix column operations or inverse mix column operations; and
the second operations include byte substitution operations or inverse byte substitution operations.

22. A differential logic gate comprising:
a first logic gate comprising:
a first plurality of p-type field effect transistors (PFETs) coupled in series between a first output and a supply rail;
a second plurality of PFETs coupled in series between the first output and the supply rail;
a first plurality of n-type field effect transistors (NFETs) coupled in series between the first output and a ground;
a second plurality of NFETs coupled in series between the first output and the ground;
a first conduction path between a first node and a second node, wherein the first node is between two PFETs in the first plurality of PFETs and the second node is between two NFETs in the first plurality of NFETs; and
a second conduction path between a third node and a fourth node, wherein the third node is between two PFETs in the second plurality of PFETs and the fourth node is between two NFETs in the second plurality of NFETs; and

a second logic gate comprising:
a third plurality of PFETs coupled in series between a second output and the supply rail;
a fourth plurality of PFETs coupled in series between the second output and the supply rail;
a third plurality of NFETs coupled in series between the second output and the ground; and
a fourth plurality of NFETs coupled in series between the second output and the ground; a

Assignees

• Qualcomm Inc

Inventors

• Ramaraju Ravindraraj
• Vattikonda Rakesh
• Sinharoy Samrat
• Lu de
• Pang Bo

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L2209/125

  Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations · CPC title