Chained bus memory device

Patent metadata

Field	Value
Publication number	US-10664411-B2
Application number	US-201715470590-A
Country	US
Kind code	B2
Filing date	Mar 27, 2017
Priority date	Aug 15, 2008
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

First claim

What is claimed is:

1. A memory device comprising:
a normally enabled upstream data input port;
a selectively enabled upstream data output port, wherein the upstream data output port is initially disabled, wherein communication is allowed via the upstream data output port when the upstream data output port is enabled, and wherein communication is not allowed via the upstream data output port when the upstream data output port is disabled;
a normally enabled downstream data input port;
a selectively enabled downstream data output port, wherein the downstream data output port is initially disabled, wherein communication is allowed via the downstream data output port when the downstream data output port is enabled, and wherein communication is not allowed via the downstream data output port when the downstream data output port is disabled; and
operational circuitry in the memory device, the operational circuitry configured to perform operations comprising:
enabling the upstream data output port and then communicating via the upstream data output port to an external host that an identifier has been assigned to the memory device; and
upon receipt of external host instructions via the upstream data input port, enabling the downstream data output port and then monitoring the downstream data input port for a signal indicative of the presence of a downstream memory device.

2. The memory device of claim 1 , wherein the upstream data output port is disabled until used to communicate to the external host that the identifier has been assigned to the memory device.

3. The memory device of claim 1 , wherein the operations comprise enabling the downstream data output port upon receipt of the external host instructions after an identifier has been assigned to the memory device.

4. The memory device of claim 1 , wherein the operations further comprise booting with a known default identifier before any subsequent identifier is assigned.

5. The memory device of claim 1 , wherein the operations further comprise at least partially performing clock training and synchronization before an identifier is assigned.

6. A memory device comprising:
an upstream data input port;
an upstream data output port;
a downstream data input port;
a downstream data output port; and
a local storage device contained entirely within the memory device, the local storage device configured to store information that indicates whether or not a downstream memory device is present.

7. The memory device of claim 6 , further including operational circuitry to perform clock training and synchronization prior to receiving an identifier from a host.

8. The memory device of claim 6 , further including operational circuitry to record the presence or absence of a downstream device as the information in the local storage device.

9. The memory device of claim 6 , wherein the local storage device includes a register.

10. The memory device of claim 6 , wherein the upstream data output port is disabled until used to communicate to an external host that an identifier has been assigned to the memory device.

11. The memory device of claim 6 , further including operational circuitry in the memory device, wherein the operational circuitry is configured to disable the downstream data output port upon power up of the memory device, and configured to enable the downstream data output port upon receipt of external host instructions after an identifier has been assigned to the memory device.

12. The memory device of claim 11 , wherein the operational circuitry is further configured to boot with a known default identifier before any subsequent identifier is assigned.

13. A memory device comprising:
a normally enabled upstream data input port;
a selectively enabled upstream data output port, wherein the upstream data output port is initially disabled, wherein communication is allowed via the upstream data output port when the upstream data output port is enabled, and wherein communication is not allowed via the upstream data output port when the upstream data output port is disabled;
a normally enabled downstream data input port;
a selectively enabled downstream data output port, wherein the downstream data output port is initially disabled, wherein communication is allowed via the downstream data output port when the downstream data output port is enabled and wherein communication is not allowed via the downstream data output port when the downstream data output port is disabled; and
operational circuitry in the memory device configured to perform operations comprising enabling the upstream data output port and the downstream data output port after a first identifier is assigned to the memory device.

14. The memory device of claim 13 , wherein the operations further comprise at least partially performing startup operations before the first identifier is assigned to the memory device.

15. The memory device of claim 13 , wherein the operations further comprise at least partially performing clock training and synchronization before the first identifier is assigned to the memory device.

16. The memory device of claim 13 , wherein the operations further comprise booting with a known default identifier before the first identifier is assigned to the memory device.

17. The memory device of claim 13 , wherein the operations further comprise disabling the downstream data output port if it is determined that there is no downstream device present.

18. The memory device of claim 13 , wherein the upstream data output port is disabled until used to communicate to an external host that the first identifier has been assigned to the memory device.

19. The memory device of claim 13 , wherein the operations further comprise detecting a presence or absence of a downstream device by monitoring for a signal via the downstream data input port, the operations further comprising recording the presence or absence of a downstream device in a local storage device of the memory device.

20. The memory device of claim 13 , further including a local storage device contained entirely within the memory device, the local storage device configured to store information that Moil indicates whether or not a downstream memory device is present.

Assignees

• Micron Technology Inc

Inventors

• Tsai Victor
• Radke William Henry
• Leibowitz Bob

Classifications

• G06F11/3034

  where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4208

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title