Chained bus method

Patent metadata

Field	Value
Publication number	US-9606885-B2
Application number	US-201314053255-A
Country	US
Kind code	B2
Filing date	Oct 14, 2013
Priority date	Aug 15, 2008
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

First claim

What is claimed is:

1. A method, comprising:
assigning a first identifier to an upstream device in a chain of devices;
determining whether there is a downstream device in the chain that is downstream of the device that was assigned the first identifier;
enabling an upstream data output port on the upstream device after assigning the first identifier;
enabling a downstream data output port on the upstream device after assigning the first identifier; and
assigning a second identifier to the downstream device in the chain at least partially in response to determining that the downstream device is present.

2. The method of claim 1 , wherein assigning the first identifier to the upstream device in the chain includes assigning a first identifier to a memory device in the chain.

3. The method of claim 2 , further including powering up sequential memory devices one at a time and assigning identifiers as each memory device is powered up.

4. The method of claim 2 , wherein determining comprises enabling the downstream data output port on the upstream device and determining whether a signal is received on a downstream data input port from the downstream device.

5. The method of claim 2 , further including powering up all devices in the chain and performing start up operations at least partially before assigning identifiers sequentially.

6. The method of claim 5 , wherein performing start up operations includes performing clock training and synchronization.

7. The method of claim 6 , wherein determining whether there is a downstream device includes detecting whether a signal is received on a downstream data input port from the downstream device.

8. The method of claim 7 , further including storing an indication of a presence or absence of the downstream device in a storage device in the upstream device.

9. The method of claim 2 , further comprising booting each device in the chain with a known identifier.

10. The method of claim 9 , wherein the known identifier is one of a default identifier and an identifier of a last memory device in a chain at a downstream end.

11. The method of claim 10 , wherein assigning the first identifier and the second identifier comprises changing the default identifier to the first identifier and the second identifier in a sequential manner.

12. The method of claim 2 , further comprising storing an indication of a presence or absence of a downstream device in a respective storage device associated with each of the devices.

13. The method of claim 2 , wherein determining whether there is a downstream device comprises determining whether the downstream device is configured in such a way as to indicate that it is a last device in the chain of devices.

14. The method of claim 13 , wherein determining whether the memory device is configured in such a way as to indicate that it is a last device in the chain of devices comprises determining whether the downstream device does not have a downstream port.

15. The method of claim 2 , further comprising disabling a downstream port of the upstream device if it is determined that there is no device in the chain that is downstream of the upstream device.

16. The method of claim 2 , further comprising enabling an upstream output of the downstream device before assigning the second identifier.

17. The method of claim 2 , further comprising enabling a downstream output of the downstream device after assigning the second identifier.

18. A method, comprising:
incrementally powering up each memory device a memory device chain, including;
enabling an upstream input port and an upstream output port on an upstream memory device;
assigning a unique identifier to the upstream memory device;
enabling an upstream data output port on the upstream device after assigning the unique identifier;
detecting when no additional downstream devices are present by enabling a downstream data output port on the upstream memory device and determining whether a signal is received on a downstream data input port on the upstream memory device from a downstream memory device; and
disabling the downstream output port on the upstream memory device if no downstream memory device is detected.

19. The method of claim 18 , wherein only a last memory device in the memory device chain communicates back to a host device, and the host device determines how many total memory devices are present.

20. The method of claim 18 , wherein the downstream output port on the upstream memory device is enabled after the unique identifier is assigned to the upstream memory device.

Assignees

• Micron Technology Inc

Inventors

• Tsai Victor
• Radke William Henry
• Leibowitz Bob

Classifications

• G06F13/4208

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F3/007

  Digital input from or digital output to memories of the shift register type · CPC title