Multiple core analysis mode for defect analysis

Patent metadata

Field	Value
Publication number	US-10664370-B2
Application number	US-201815969273-A
Country	US
Kind code	B2
Filing date	May 2, 2018
Priority date	Jun 28, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first arithmetic core configured to execute a first program stored in a first code area using a first local memory area;
a second arithmetic core configured to execute a second program stored in a second code area different from the first code area using a second local memory area;
an analysis code area configured to store an analysis control program;
an analysis local memory area configured to hold an execution result of the analysis control program;
an analysis core configured to control a program execution state of the first arithmetic core or the second arithmetic core based on the analysis control program in an analysis mode in which a defect in the first arithmetic core and the second arithmetic core is analyzed; and
an access path control unit configured to, in a normal operation mode in which the first arithmetic core and the second arithmetic core independently operate, prevent the first arithmetic core from accessing the second code area and the second arithmetic core from accessing the first code area, wherein
in the analysis mode, the access path control unit switches an access path so that the first program is read into the first arithmetic core and the second arithmetic core in accordance with a command from the analysis core in first analysis processing and switches the access path so that the second program is read into the first arithmetic core and the second arithmetic core in second analysis processing, and
the analysis core compares, in the first analysis processing, first arithmetic result data generated by the first arithmetic core based on the first program with second arithmetic result data generated by the second arithmetic core based on the first program and, in the second analysis processing, compares third arithmetic result data generated by the first arithmetic core based on the second program with fourth arithmetic result data generated by the second arithmetic core based on the second program in order to generate analysis information used for analyzing the defect in the first arithmetic core, the second arithmetic core, and circuits used by the first arithmetic core and the second arithmetic core.

2. The semiconductor device according to claim 1 , wherein
the analysis code area stores a core analysis program that executes a specific test sequence on the first arithmetic core and the second arithmetic core, and
in a debugging mode, the analysis core causes the first arithmetic core and the second arithmetic core to execute the core analysis program and generates the analysis information based on fifth arithmetic result data generated based on the core analysis program.

3. The semiconductor device according to claim 1 , wherein the access path control unit comprises a path setting register that holds a path setting value provided by the analysis core and switches a code area to be an access destination of the first arithmetic core and the second arithmetic core based on the path setting value.

4. The semiconductor device according to claim 1 , further comprising a debugger configured to instruct the analysis core to start an operation based on the analysis control program.

5. The semiconductor device according to claim 1 , further comprising a plurality of peripheral circuits connected to the first arithmetic core and the second arithmetic core via a bus, wherein the first arithmetic core and the second arithmetic core execute the first program or the second program using at least one of the plurality of peripheral circuits in the analysis mode.

6. The semiconductor device according to claim 5 , wherein the plurality of peripheral circuits include at least one of a timer, an analog-to-digital conversion circuit, a coprocessor, a memory, a direct memory access controller, a PWM signal generation circuit, a communication interface circuit, and an input and output interface circuit.

7. The semiconductor device according to claim 1 , wherein
each of the first arithmetic core and the second arithmetic core comprises a ring buffer,
the ring buffer acquires signals input to and output from the first arithmetic core and the second arithmetic core in chronological order and holds them as operation monitor information, and
the first arithmetic result data to the fourth arithmetic result data include the operation monitor information held in the ring buffer.

8. The semiconductor device according to claim 1 , further comprising:
a third arithmetic core configured to execute a third program stored in a third code area different from the first code area and the second code area using a third local memory area; and
a debugger configured to instruct the first arithmetic core to the third arithmetic core to perform or not to perform an operation based on the analysis mode, wherein the third arithmetic core operates as the analysis core in accordance with the command from the debugger in the analysis mode.

9. The semiconductor device according to claim 8 , wherein the access path control unit comprises an analysis master setting register for holding an analysis master setting value provided from the debugger and switches a code area of an access destination of the third arithmetic core to the analysis code area based on the analysis master setting value.

10. The semiconductor device according to claim 8 , wherein
the analysis local memory area is a global memory area, which is one of peripheral circuits accessible from the first arithmetic core, the second arithmetic core, and the third arithmetic core, and
the third arithmetic core loads the analysis control program from the global memory area based on the analysis master setting value provided from the debugger in order to function as the analysis core.

11. The semiconductor device according to claim 1 , wherein
each of the first arithmetic core and the second arithmetic core comprises:
a master core and a slave core having the same circuit configuration;
a plurality of ring buffers provided to respectively correspond to each of the master core and the slave core;
a local memory area shared by the first arithmetic core and the second arithmetic core;
a comparison setting register configured to store a buffer comparison setting value specifying a combination of output values of the ring buffers to be compared; and
a ring buffer comparison unit configured to compare the output values of the ring buffers according to the combination of the output values of the ring buffers specified based on the buffer comparison setting value and output an error signal when there is a mismatch between the output values,

in the analysis mode, the analysis core rewrites the buffer comparison setting value so that the output values of the ring buffers belonging to different arithmetic cores are compared, and
at the end of the analysis mode, the analysis core writes back the buffer comparison setting value so that the output values of the ring buffers belonging to the same arithmetic core are compared.

12. The semiconductor device according to claim 11 , further comprising a debugger configured to, in the normal operation mode, instruct the analysis core to start an operation in the analysis mode based on the error signal output from the ring buffer comparison unit.

Assignees

• Renesas Electronics Corp

Inventors

• Shiozawa Kenji
• Nakamura Yoshihide
• Lee Takuya
• Nakadai Yutaka
• Kokubun Tetsuya
• Sasaki Hiroyuki

Classifications

• G06F11/277 Primary

  with comparison between actual response and known fault-free response · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G06F11/1629

  Error detection by comparing the output of redundant processing systems · CPC title

• G06F11/26 Primary

  Functional testing · CPC title

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title