Data transfers with adaptively adjusted polling times

Patent metadata

Field	Value
Publication number	US-10664168-B2
Application number	US-201816201767-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	May 26, 2017
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

First claim

What is claimed is:

1. An apparatus comprising:
a memory module comprising a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM;
a statistics table configured to store accumulated statistics of a history of data transfer command wait periods associated with a subset of the memory cells of the NVM; and
a controller circuit configured to issue data transfer commands at a first delay rate to the MME circuit, each command including an address within a range of addresses of the subset of the memory cells and a data transfer action to be taken by the MME circuit in relation to the included address, the controller circuit further configured to analyze the stored statistics of the statistics table and adjust the first delay rate to a second delay rate based on the analyzing, the controller circuit further configured to issue further data transfer commands at the second delay rate to the MME circuit in relation to the subset of the memory cells.

2. The apparatus of claim 1 , wherein the controller circuit is further configured to accumulate statistics to store in the statistics table by issuing status requests to the MME circuit and receiving a response.

3. The apparatus of claim 2 , wherein accumulating statistics comprises accumulating “not ready” responses to status requests.

4. The apparatus of claim 1 , wherein the data transfer command wait periods represent a time interval from issuance of a command to a subsequent communication of a “ready” response.

5. The apparatus of claim 1 , further comprising an environmental sensor configured to sense an ambient temperature range of the NVM and wherein the statistics table is configured to store the accumulated history statistics in association with the sensed ambient temperature range, the controller circuit further configured to analyze for a current sensed ambient temperature range.

6. The apparatus of claim 1 , wherein the controller circuit is configured to analyze by interpolating an average of data transfer command wait periods.

7. The apparatus of claim 1 , wherein the controller circuit is further configured to adjust the first delay rate by factoring environmental factors into the adjustment.

8. The apparatus of claim 7 , wherein the environmental factors comprise aging and read disturb effects.

9. The apparatus of claim 1 , wherein the NVM comprises a NAND flash memory array comprising a plurality of dies, and wherein the selected address comprises a selected die from the plurality of dies.

10. The apparatus of claim 9 , further comprising a delay table stored as a data structure in a local memory, the delay table providing the controller circuit with a different variable delay time interval for each of the plurality of dies.

11. A method comprising:
issuing data transfer commands at a first delay rate to a memory module electronics (MME) circuit, each command including an address within a range of addresses of a subset of the memory cells of a solid-state non-volatile memory (NVM) and a data transfer action to be taken by the MME circuit in relation to the included address;
accumulating statistics of a history of data transfer command wait periods associated with the subset;
storing the accumulated history statistics as a statistics table in a data structure in local memory;
analyzing the stored statistics;
adjusting the first delay rate to a second delay rate based on the analyzing; and
issuing further data transfer commands at the second delay rate to the MME circuit in relation to the subset of the memory cells.

12. The method of claim 11 , wherein accumulating statistics comprises issuing status requests to the MME circuit and receiving a response.

13. The method of claim 12 , wherein accumulating statistics comprises accumulating “not ready” responses to status requests.

14. The method of claim 11 , wherein the data transfer command wait periods represent a time interval from issuance of a command to a subsequent communication of a “ready” response.

15. The method of claim 11 , wherein accumulating history statistics comprises accumulating command completion time performance of the NVM.

16. The method of claim 11 , wherein analyzing comprises interpolating an average of data transfer command wait periods.

17. The method of claim 11 , wherein analyzing comprises using an accumulated count mask bit to leave out known errant counts of data transfer command wait periods.

18. The method of claim 11 , wherein adjusting the first delay rate further comprises factoring environmental factors into the adjustment.

19. The method of claim 18 , wherein the environmental factors comprise aging and read disturb effects.

20. The method of claim 11 , wherein adjusting the first delay rate comprises determining a baseline delay value based on retrieval of lower page single level cell data from a set of cells and adding an additional delay to the baseline delay value to account for additional time to retrieve higher page data from the same set of cells.

Assignees

• Seagate Technology Llc

Inventors

• Canepa Timothy
• Hanna Stephen

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title