Access node integrated circuit for data centers which includes a networking unit, a plurality of host units, processing clusters, a data network fabric, and a control network fabric

Patent metadata

Field	Value
Publication number	US-10659254-B2
Application number	US-201816031676-A
Country	US
Kind code	B2
Filing date	Jul 10, 2018
Priority date	Jul 10, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.

First claim

What is claimed is:

1. An access node integrated circuit comprising:
a networking unit configured to control input and output of data between a network and the access node integrated circuit;
one or more host units configured to at least one of control input and output of the data between the access node integrated circuit and one or more application processors or control storage of the data with one or more storage devices;
a plurality of processing clusters, each of the processing clusters including two or more programmable processing cores configured to perform processing tasks on the data;
a data network fabric interconnecting the plurality of processing clusters, the one or more host units, and the networking unit, wherein the data network fabric is configured to carry the data between the networking unit, the one or more host units, and the plurality of processing clusters; and
at least one control network fabric interconnecting the plurality of processing clusters, the one or more host units, and the networking unit, wherein the at least one control network fabric is configured to carry control messages identifying the processing tasks to be performed on the data by the programmable processing cores of the plurality of processing clusters.

2. The access node integrated circuit of claim 1 , wherein each of the processing clusters comprises:
a coherent cache memory implemented in circuitry; and
a non-coherent buffer memory implemented in circuitry,
wherein each of the programmable processing cores of the respective processing cluster are connected to the coherent cache memory and the non-coherent buffer memory.

3. The access node integrated circuit of claim 2 , wherein each of the programmable processing cores is configured to store stream data in the non-coherent buffer memory and store other data in the coherent cache memory, wherein the stream data comprises packets of network transmission data.

4. The access node integrated circuit of claim 2 , wherein each of the programmable processing cores of each of the processing clusters comprises:
a plurality of virtual processors;
a level one (L1) data cache memory for caching coherent data; and
a L1 buffer cache memory for caching non-coherent data.

5. The access node integrated circuit of claim 4 , wherein each of the programmable processing cores is configured to cache the stream data in the L1 buffer cache memory and cache other data in the L1 data cache memory, wherein the stream data comprises packets of network transmission data.

6. The access node integrated circuit of claim 4 , wherein, to perform processing tasks on the data, at least one processing cluster of the plurality of processing clusters is configured to:
receive a work unit indicating a processing task to be performed on the data;
determine one of the programmable processing cores to perform the processing task;
send the work unit to a queue associated with a virtual processor of the plurality of virtual processors of the one of the programmable processing cores; and
receive results of the processing task from the one of the programmable processing cores.

7. The access node integrated circuit of claim 6 , wherein, to perform the processing task on the data, the virtual processor of the plurality of virtual processors is configured to:
receive the work unit from the associated queue indicating the processing task to be performed on the data;
fetch the data from one of the L1 data cache memory or the L1 buffer cache memory of the one of the programmable processing cores;
perform the indicated processing task on the data; and
output the results of the processing task including one or more work unit messages.

8. The access node integrated circuit of claim 1 , wherein each of the processing clusters further comprises one or more accelerator units implemented in circuitry, and wherein the one or more accelerator units comprise hardware implementations of one or more of a lookup engine, a matrix multiplier, a cryptographic engine, a compression engine, or a regular expression interpreter.

9. The access node integrated circuit of claim 1 , wherein each of the programmable processing cores of each of the processing clusters comprises one of a MIPS (microprocessor without interlocked pipeline stages) core, an ARM (advanced RISC (reduced instruction set computing) machine) core, a PowerPC (performance optimization with enhanced RISC—performance computing) core, a RISC-V (RISC five) core, or a CISC (complex instruction set computing or x86) core.

10. The access node integrated circuit of claim 1 , wherein each of the programmable processing cores is programmable using a high-level programming language.

11. The access node integrated circuit of claim 1 , wherein the plurality of processing clusters includes a central cluster implemented in circuitry.

12. The access node integrated circuit of claim 11 , wherein the central cluster comprises:
a central dispatch unit configured to perform flow control, select one of the processing clusters to perform work units, and dispatch work units to the selected one of the processing clusters;
a coherence directory unit configured to determine locations of data within coherent cache memory of the access node integrated circuit; and
a central synchronization unit configured to maintain proper sequencing and ordering of operations within the access node integrated circuit.

13. The access node integrated circuit of claim 1 , wherein the networking unit is configured to support Ethernet interfaces to connect directly to the network without a separate network interface card (NIC).

14. The access node integrated circuit of claim 1 , wherein the networking unit is configured as a network switch to send and receive network data for the access node integrated circuit.

15. The access node integrated circuit of claim 1 , wherein the networking unit comprises a network packet parsing unit configured to parse network packets.

16. The access node integrated circuit of claim 1 , wherein the one or more host units are each configured to support PCI-e (Peripheral Component Interconnect-Express) interfaces to connect directly to the application processors and the storage devices.

17. The access node integrated circuit of claim 1 , wherein the data network fabric is formed by grid links between the plurality of processing clusters, the networking unit, the one or more host units, and an external memory.

18. The access node integrated circuit of claim 17 , wherein the data network fabric comprises a two-dimensional mesh topology, and wherein the data network fabric is configured to carry coherent memory data and non-coherent memory data.

19. The access node integrated circuit of claim 1 , wherein the at least one control network fabric includes a signaling network formed by a set of direct links between a central cluster of the plurality of processing clusters and each of the other processing clusters, the networking unit, the one or more host units, and an external memory, wherein the signaling network transports control messages related to non-coherent streaming data.

20. The access node integrated circuit of claim 19 , wherein the signaling network comprises a non-blocking, switched, low latency fabric, and wherein the signaling network is configured to carry flow control messages, resource status messages, work unit delivery messages, and work scheduling messages to the processing clusters.

21. The access node integrated circuit of claim 19 , wh

Assignees

• Fungible Inc

Inventors

• Sindhu Pradeep
• Frailong Jean-Marc
• Serlet Bertrand
• Noureddine Wael
• Marti Felix A
• Goel Deepak
• Kim Paul
• Goyal Rajan
• Zhou Aibing

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• H04L49/253

  using establishment or release of connections between ports · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• H04L2012/5681

  Buffer or queue management · CPC title