Multi-port PUF circuit based on MOSFET current division deviations

Patent metadata

Field	Value
Publication number	US-10659238-B2
Application number	US-201816043140-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Aug 16, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1 st inverter, a 2 nd inverter, a 3 rd inverter, a 4 th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The m th output terminal of the row decoder is connected to the m th row selective signal input terminals of the 32 PUF arrays. The j th output terminal of the column decoder is connected to the j th selective signal input terminals of the 32 PUF arrays. The 1 st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2 nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

First claim

What is claimed is:

1. A MULTI-PORT PUF CIRCUIT BASED ON MOSFET CURRENT DIVISION DEVIATIONS, CHARACTERIZED IN THAT COMPRISES:
a reference source, comprising a 1 st voltage output terminal, a 2 nd voltage output terminal, a 3 rd voltage output terminal and a current output terminal;
a row decoder, comprising a control terminal, 128 input terminals and 7 output terminals;
a column decoder, comprising a control terminal, 2 input terminals and 4 output terminals
a timing controller, comprising a 1 st output terminal and a 2 nd output terminal;
32 PUF arrays, comprises a 512 PUF cells, an arbiter, a 1 st inverter, a 2 nd inverter, a 3 rd inverter, a 4 th inverter and 8 transmission gates, wherein each transmission gate is provided with a 1 st control terminal, a 2 nd control terminal, an input terminal and an output terminal;
wherein the 8 transmission gates are a 1 st transmission gate, a 2 nd transmission gate, a 3 rd transmission gate, a 4 th transmission gate, a 5 th transmission gate, a 6 th transmission gate, a 7 th transmission gate and an 8 th transmission gate;

wherein the arbiter is configured with a 1 st input terminal, a 2 nd input terminal, a 1 st bias terminal, a 2 nd bias terminal and an output terminal;
wherein each of the PUF cell is comprises a control voltage input terminal, a control current input terminal, a selective signal input terminal, a 1 st output terminal and a 2 nd output terminal;
wherein the 512 PUF cells are arranged in 128 rows and 4 columns and the control voltage input terminals of the 512 PUF cells are coupled;
wherein a connecting terminal is a 1 st control voltage input terminal of the corresponding PUF array, the control current input terminals of the 512 PUF cells are coupled, the connecting terminal is the control current input terminal of the corresponding PUF array,
wherein the selective signal input terminals of the PUF cells in the m th row are coupled, the connecting terminal is the m th row selective signal input terminal of the corresponding PUF array, and m=1, 2, . . . , 128,
wherein the 1 st output terminals of the PUF cells in a 1 st column are connected to an input terminal of the 1 st transmission gate, the 2 nd output terminals of the PUF cells in the 1 st column are coupled to an input terminal of the 2 nd transmission gate, the 1 st output terminals of the PUF cells in the 2 nd column are coupled to an input terminal of the 3 rd transmission gate, the 2 nd output terminals of the PUF cells in the 2 nd column are coupled to an input terminal of the 4 th transmission gate, the 1 st output terminals of the PUF cells in the 3 rd column are coupled to an input terminal of the 5 th transmission gate, the 2 nd output terminals of the PUF cells in the 3 rd column are coupled to the input terminal of the 6 th transmission gate, the 1 st output terminals of the PUF cells in the 4 th column are coupled to an input terminal of the 7 th transmission gate, and the 2 nd output terminals of the PUF cells in the 4 th column are connected to an input terminal of the 8 th transmission gate;
wherein the 1 st control terminal of the 1 st transmission gate and the 1 st control terminal of the 2 nd transmission gate are connected to the input terminal of the 1 st inverter, the connecting terminal is the 1 st column selective signal input terminal of the corresponding PUF array,
wherein the 2 nd control terminal of the 1 st transmission gate and the 2 nd control terminal of the 2 nd transmission gate are coupled to an output terminal of the 1 st inverter, the 1 st control terminal of the 3 rd transmission gate and a 1 st control terminal of the 4 th transmission gate are coupled to an input terminal of the 2 nd inverter, the connecting terminal is the 2 nd column selective signal input terminal of the corresponding PUF array,
wherein the 2 nd control terminal of the 3 rd transmission gate and the 2 nd control terminal of the 4 th transmission gate are coupled to an output terminal of the 2 nd inverter, the 1 st control terminal of the 5 th transmission gate and the 1 st control terminal of the 6 th transmission gate are connected to the input terminal of the 3 rd inverter, the connecting terminal is the 3 rd column selective signal input terminal of the corresponding PUF array,
wherein the 2 nd control terminal of the 5 th transmission gate and the 2 nd control terminal of the 6 th transmission gate are coupled to an output terminal of the 3 rd inverter; the 1 st control terminal of the 7 th transmission gate and the 1 st control terminal of the 8 th transmission gate are coupled to an input terminal of the 4 th inverter, the connecting terminal is the 4 th column selective signal input terminal of the corresponding PUF array,
wherein the 2 nd control terminal of the 7 th transmission gate and the 2 nd control terminal of the 8 th transmission gate are coupled to an output terminal of the 4 th inverter;
wherein an output terminal of the 1 st transmission gate, an output terminal of the 3 rd transmission gate, an output terminal of the 5 th transmission gate and an output terminal of the 7 th transmission gate are coupled to a 1 st input terminal of the arbiter; an output terminal of the 2 nd transmission gate, an output terminal of the 4 th transmission gate, an output terminal of the 6 th transmission gate and an output terminal of the 8 th transmission gate are coupled to a 2 nd input terminal of the arbiter;
wherein the 1 st bias terminal of the arbiter is a 2 nd control voltage input terminal of the corresponding PUF array, and a 2 nd bias terminal of the arbiter is a 3 rd control voltage input terminal of the corresponding PUF array,
wherein the 1 st voltage output terminal of the reference source is coupled to the 1 st control voltage input terminals of the PUF arrays, the 2 nd voltage output terminal of the reference source is coupled to the 2 nd control voltage input terminals of the 32 PUF arrays, the 3 rd voltage output terminal of the reference source is coupled to a 3 rd control voltage input terminals of the 32 PUF arrays, and the current output terminal of the reference source is coupled to a control current input terminal of the 32 PUF arrays,
wherein a m th output terminal of the row decoder is coupled to a m th row selective signal input terminals of the 32 PUF arrays, a j th output terminal of the column decoder is coupled to the j th column selective signal input terminals of the 32 PUF arrays, and j=1, 2, 3, 4;
wherein a 1 st output terminal of the timing controller is coupled to a control terminal of the row decoder, and a 2 nd output terminal of the timing controller is coupled to a control terminal of the column decoder.

2. A multi-port PUF circuit based on MOSFET current division deviations according to claim 1 , wherein each PUF cell comprises a 1 st NMOS transistor, a 2 nd NMOS transistor, a 3 rd NMOS transistor and a 4 th NMOS transistor,
wherein a drain of the 1 st NMOS transistor is connected to a drain of the 2 nd NMOS transistor, and the connecting terminal is the control current input terminal of the PUF cell, a gate of the 1 st NMOS transistor is coupled to a gate of the 2 nd NMOS transistor, and the connecting terminal is the control voltage input terminal of the PUF cell; a source of the 1 st NMOS transistor is coupled to a drain of the 3 rd NMOS transistor, a the source of the 2 nd NMOS transistor is coupled to a drain of the 4 th NMOS transistor, a source of the 3 rd NMOS transistor is the 1 st output terminal of the PUF cell, and the source of the 4 th NMOS transistor is the 2 nd output terminal of the PUF cell, a gate of the 3 rd NMOS transistor is coupled to a gate of the 4 th NMOS transistor, and the connecting terminal is the selective signal input terminal of t

Assignees

• Univ Ningbo

Inventors

• Wang Pengjun
• Li Gang
• Zhang Yuejun
• Zhang Huihong

Classifications

• G06F21/73

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title