System, Apparatus And Method For Providing A Physically Unclonable Function (PUF) Based On A Memory Technology

Patent metadata

Field	Value
Publication number	US-2017288885-A1
Application number	US-201615086207-A
Country	US
Kind code	A1
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Oct 5, 2017
Grant date	—

Abstract

In one embodiment, an apparatus comprises: a challenger logic to issue a challenge to a responder logic, the challenge including an address of a portion of an array of a non-volatile memory; and the responder logic to receive the challenge and read data from the portion of the array at a read time less than a lockout period and at a demarcation voltage. The challenger logic may be configured to verify the challenge if the read data matches an expected read value, where the expected read value is determined based on configuration parameter information including compensation data associated with the portion of the array. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a challenger logic to issue a challenge to a responder logic, the challenge including an address of a portion of an array of a non-volatile memory; and the responder logic to receive the challenge and read data from the portion of the array at a read time less than a lockout period and at a demarcation voltage; wherein the challenger logic is to verify the challenge if the read data matches an expected read value, the challenger logic to determine the expected read value based on configuration parameter information including compensation data associated with the portion of the array.

2 . The apparatus of claim 1 , wherein the responder logic is to write the data to the portion of the array responsive to the challenge and read the data from the portion of the array prior to completion of the lockout period following the write.

3 . The apparatus of claim 1 , wherein the challenger logic is to indicate the read time and the demarcation voltage to the responder logic, wherein at least one of the demarcation voltage and the read time is randomly determined by the challenger logic.

4 . The apparatus of claim 1 , wherein the challenge comprises a one time password.

5 . The apparatus of claim 1 , wherein the non-volatile memory comprises a phase change memory.

6 . The apparatus of claim 1 , wherein the read data comprises a multi-bit value.

7 . The apparatus of claim 6 , wherein the challenger logic is to verify the challenge if the multi-bit value of the read data matches a multi-bit value of the expected read value to at least a threshold level.

8 . The apparatus of claim 1 , wherein the read data differs from a stored value in the portion of the array, after the lockout period has completed.

9 . The apparatus of claim 1 , further comprising a memory controller including the challenger logic and the responder logic, the challenger logic and the responder logic comprising general-purpose circuitry of the memory controller.

10 . The apparatus of claim 9 , wherein the apparatus comprises a system on chip (SoC), the SoC including the non-volatile memory and the memory controller.

11 . The apparatus of claim 10 , wherein the SoC comprises a first semiconductor die including the non-volatile memory and a second semiconductor die including the memory controller.

12 . The apparatus of claim 9 , wherein the SoC comprises a security logic to request the challenge after a reset, and wherein the security logic is to prevent normal operation of the SoC if the challenger logic does not verify the challenge.

13 . At least one computer readable storage medium comprising instructions that when executed enable a system to:
issue a challenge to a responder, the challenge including an address of a cell of a non-volatile memory and associated with a read time and a demarcation voltage, wherein at least one of the read time and the demarcation voltage is outside a legal range; identify a read value obtained from the responder, responsive to the challenge; generate an expected value for the read value based at least in part on configuration parameter information associated with the cell; and report a result of the challenge based at least in part on a comparison between the read value and the expected value.

14 . The at least one computer readable storage medium of claim 13 , further comprising instructions that when executed enable the system to access the cell configuration parameter information from a compensation table stored in the non-volatile memory.

15 . The at least one computer readable storage medium of claim 13 , further comprising instructions that when executed enable the system to communicate the read time and the demarcation voltage to the responder, wherein at least one of the read time and the demarcation voltage comprises a randomly generated value.

16 . The at least one computer readable storage medium of claim 15 , further comprising instructions that when executed enable the system to communicate the read time having a value less than a lockout period associated with the non-volatile memory.

17 . The at least one computer readable storage medium of claim 13 , further comprising instructions that when executed enable the system to report the result to a security logic of the system, the security logic to enable the system responsive to a valid signature indicated by the report and disable the system responsive to an invalid signature indicated by the report.

18 . A system on chip (SoC) comprising:
a non-volatile memory including a plurality of cells, at least some the plurality of cells to store compensation data for the non-volatile memory; and a memory controller to couple to the non-volatile memory, the memory controller comprising:
a first logic to issue a challenge including an address of a cell of the plurality of cells, the challenge associated with a read time and a demarcation voltage, wherein at least one of the read time and the demarcation voltage is outside of a legal range; and
a second logic, responsive to the challenge, to read data from the cell at the read time and the demarcation voltage, wherein the first logic is to verify the challenge if the read data matches an expected read value, the expected read value based on the compensation data associated with the cell.

19 . The SoC of claim 18 , wherein the second logic is to read the data from the cell prior to completion of a lockout period following a write to the cell, the read time within the lockout period.

20 . The SoC of claim 18 , wherein the first logic is to randomly generate at least one of the read time and the demarcation voltage, to enable the challenge to emulate a physically unclonable function.

Assignees

• Intel Corp

Inventors

• Khatib Zadeh Amirali
• Qawami Shekoufeh
• Maiti Abhranil

Classifications

• G06F2212/1052

  Security improvement · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F12/1466

  Key-lock mechanism · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title